Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication
First Claim
Patent Images
1. A method for fabricating a memory array comprising:
- forming a first conductor level of spaced-apart, parallel, generally coplanar conductors extending in a first direction;
forming a layer stack for defining memory elements on the first conductor level;
patterning the layer stack into a plurality of pillars;
forming a second conductor level of spaced-apart, parallel, generally coplanar conductors extending in a second direction, said second direction not parallel to said first direction;
any of said plurality of pillars comprising an anti-fuse layer, said anti-fuse layer positioned between a pair of diode components that form a diode only after the anti-fuse layer is disrupted.
6 Assignments
0 Petitions
Accused Products
Abstract
A three-dimensional, field-programmable, non-volatile memory includes multiple layers of first and second crossing conductors. Pillars are self-aligned at the intersection of adjacent first and second crossing conductors, and each pillar includes at least an anti-fuse layer. The pillars form memory cells with the adjacent conductors, and each memory cell includes first and second diode components separated by the anti-fuse layer. The diode components form a diode only after the anti-fuse layer is disrupted.
17 Citations
10 Claims
-
1. A method for fabricating a memory array comprising:
-
forming a first conductor level of spaced-apart, parallel, generally coplanar conductors extending in a first direction;
forming a layer stack for defining memory elements on the first conductor level;
patterning the layer stack into a plurality of pillars;
forming a second conductor level of spaced-apart, parallel, generally coplanar conductors extending in a second direction, said second direction not parallel to said first direction;
any of said plurality of pillars comprising an anti-fuse layer, said anti-fuse layer positioned between a pair of diode components that form a diode only after the anti-fuse layer is disrupted. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. A memory array comprising:
-
a plurality of first spaced-apart, parallel, substantially coplanar conductors;
a plurality of second spaced-apart, parallel, substantially coplanar conductors disposed vertically above the first conductors;
a plurality of first pillars, each first pillar vertically disposed between one of the first and one of the second conductors;
a plurality of third spaced-apart, parallel, substantially coplanar conductors disposed vertically above the second conductors; and
a plurality of second pillars, each second pillar vertically disposed between one of the second conductors and one of the third conductors, any of said pillars comprising a respective anti-fuse layer and respective first and second diode components separated by the respective anti-fuse layer, wherein any of the second conductors forms a top conductor of a lower level of cells and a bottom conductor of a top level of cells, wherein the memory array is created by a method comprising;
forming the plurality of first conductors;
forming a layer stack on the plurality of first conductors;
patterning the layer stack into the plurality of first pillars; and
forming the plurality of second conductors.
-
Specification