Digital design using selection operations

• US 20030126579A1
• Filed: 06/14/2002
• Published: 07/03/2003
• Est. Priority Date: 06/15/2001
• Status: Active Grant

• Current Assignee: Scientific Technologies Incorporated
• Original Assignee: Scientific Technologies Incorporated
• Inventors: Cameron, Eric G., Miles, Lowell H., Whitaker, Sterling R.
• Granted Patent: US 6,792,589 B2
• Time in Patent Office: Days
• US Class Current: 716/18
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/343 Logical level
• CPC Class Codes: H04L 67/06 specially adapted for file transfer, e.g. file transfer protocol [FTP]
• CPC Class Codes: H04L 67/10 in which an application is distributed across nodes in the network software deployment G06F8/60; multiprogramming arrangements G06F9/46
• CPC Class Codes: H04L 69/329 in the application layer [OSI layer 7]
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A digital integrated circuit chip is designed by identifying a logical structure to be implemented. This logical structure is represented in terms of a logical operations, at least 5% of which include selection operations. A determination is made of logic cells that correspond to an implementation of these logical operations.

Claims

1. A method for designing a digital integrated circuit chip, the method comprising:

identifying a logical structure to be implemented by the digital integrated circuit chip;

representing the logical structure in terms of a plurality of logical operations, wherein the plurality of logical operations comprises at least 5% selection operations, each such selection operation passing at least one of a plurality of inputs as an output; and

determining logic cells that correspond to an implemention of the logical operations.

2. The method recited in claim 1 wherein each such selection operation passes one of the plurality of inputs as the output.

3. The method recited in claim 1 wherein at least one of the plurality of inputs to one of the selection operations comprises a base Boolean value.

4. The method recited in claim 1 wherein at least one of the plurality of inputs to one of the selection operations comprises a higher-order function of base Boolean values.

5. The method recited in claim 1 wherein:

at least one of the logic cells corresponds to an implementation of a selection operation; and

such at least one of the logic cells comprises a multiplexor.

6. The method recited in claim 5 wherein the multiplexor comprises a depletion-mode transistor.

7. The method recited in claim 1 wherein none of the logic cells comprises a Boolean logic element having more than a single input.

8. The method recited in claim 1 further comprising performing syntactic manipulations of the logical operations.

9. The method recited in claim 1 further comprising performing syntactic manipulations of the selection operations.

10. The method recited in claim 1 wherein the plurality of logical operations comprises at least 10% selection operations.

11. The method recited in claim 1 wherein the plurality of logical operations comprises one of at least 20% selection operations, at least 30% selection operations, at least 40% selection operations, at least 50% selection operations, at least 60% selection operations, at least 70% selection operations, at least 80% selection operations, at least 90% selection operations, and at least 95% selection operations.

12. A method for designing a digital integrated circuit chip, the method comprising:

identifying a logical structure to be implemented by the digital integrated circuit chip;

representing the logical structure in terms of a plurality of logical operations wherein fewer than 50% of the plurality of logical operations comprise a Boolean logical operation having more than a single input; and

determining logic cells that correspond to an implementation of the logical operations.

13. The method recited in claim 12 wherein fewer than 25% of the plurality of logical operations comprise a Boolean logical operation having more than a single input.

14. The method recited in claim 12 wherein fewer than X% of the plurality of logical operations comprise a Boolean logical operation having more than a single input, wherein X is selected from the group consisting of 20, 15, 10, and 5.

15. The method recited in claim 12 wherein none of the plurality of logical operations comprises a Boolean logical operation having more than a single input.

16. The method recited in claim 12 wherein at least one of the logic cells comprises a depletion-mode transistor.

17. The method recited in claim 12 wherein at least one of the logic cells comprises a multiplexor.

18. A computer-readable storage medium having a computer-readable program embodied therein for directing operation of a computer system including a processor and at least one input device, wherein the computer-readable program includes instructions for operating the computer system for designing a digital circuit in accordance with the following:

receiving an expression of a logical structure to be implemented by the digital circuit from the at least one input device;

representing the logical structure in terms of a plurality of logical operations with the processor, wherein the plurality of logical operations comprises at least 5% selection operations, each such selection operation passing at least one of a plurality of inputs as an output; and

determining logic cells that correspond to an implementation of the logical operations with the processor.

19. The computer-readable storage medium recited in claim 18 wherein each such selection operation passes one of the plurality of inputs as the output.

20. The computer-readable storage medium recited in claim 18 wherein the computer readable program further includes instructions for performing syntactic manipulations of the logical operations.

21. The computer-readable storage medium recited in claim 18 wherein the computer readable program further includes instructions for performing syntactic manipulations of the selection operations.

22. The computer-readable storage medium recited in claim 21 wherein:

the computer readable program further includes instructions for receiving commands from the at least one input device; and

the syntactic manipulations of the selection operations are performed in accordance with the commands.

23. The method recited in claim 18 wherein the plurality of logical operations comprises at least 10% selection operations.

24. The method recited in claim 18 wherein the plurality of logical operations comprises one of at least 20% selection operations, at least 30% selection operations, at least 40% selection operations, at least 50% selection operations, at least 60% selection operations, at least 70% selection operations, at least 80% selection operations, at least 90% selection operations, and at least 95% selection operation.