Semiconductor device

• US 20030127678A1
• Filed: 09/09/2002
• Published: 07/10/2003
• Est. Priority Date: 01/08/2002
• Status: Active Grant

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Shimizu, Shu, Shimizu, Ippei
• Granted Patent: US 6,744,139 B2
• Time in Patent Office: Days
• US Class Current: 257/306
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator

Abstract

A semiconductor device is provided which is capable of reducing the number of masking processes in forming contact holes. The semiconductor device comprises a semiconductor substrate (1), a gate structure (9), a stopper film (11), an interlayer insulation film (12), a contact hole (17) extending from the upper surface (13) of the interlayer insulation film (12) to the semiconductor substrate (1), a metal material (18) buried in the contact hole (17), a first metal wiring layer (19), an interlayer insulation film (20), a contact hole (23) extending from the upper surface (21) of the interlayer insulation film (20) to the first metal wiring layer (19), and a contact hole (24) extending from the upper surface (21) of the interlayer insulation film (20) to a gate electrode (7) of the gate structure (9). The contact hole (24) is formed at the same time as the contact hole (23).

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a gate structure selectively formed on said semiconductor substrate and having a layered structure in which a gate electrode and an insulation film are stacked one above the other in order from said semiconductor substrate side;

an active region formed in a main surface of said semiconductor substrate;

a stopper film covering a whole surface of said gate structure and formed on said active region;

a first interlayer insulation film formed on said stopper film;

a first contact hole extending from an upper surface of said first interlayer insulation film to said active region;

a metal material buried in said first contact hole;

a metal wiring layer formed on said first interlayer insulation film to be connected to said metal material;

a second interlayer insulation film formed on said first interlayer insulation film to cover said metal wiring layer;

a second contact hole extending from an upper surface of said second interlayer insulation film through said first interlayer insulation film, said stopper film and said insulation film to said gate electrode of said gate structure; and

a third contact hole extending from the upper surface of said second interlayer insulation film to said metal wiring layer, said third contact hole being shallower than said second contact hole,

wherein an etch rate of a film in forming said second and third contact holes is larger than that of said metal wiring layer.

2. The semiconductor device according to claim 1, wherein

said insulation film and said first and second interlayer insulation films are formed of silicon oxide film,

said stopper film is formed of silicon nitride film, and

said metal wiring layer contains copper or aluminum.

3. The semiconductor device according to claim 1,

said gate structure is a gate structure of a flash memory cell.

4. The semiconductor device according to claim 2, wherein

said gate structure is a gate structure of a flash memory cell.