Dielectric structure

• US 20030128496A1
• Filed: 10/10/2002
• Published: 07/10/2003
• Est. Priority Date: 11/26/2001
• Status: Active Grant

• Current Assignee: Shipley Company, LLC (Dow, Inc.)
• Original Assignee: Shipley Company, LLC (Dow, Inc.)
• Inventors: Jacques, David L., Rzeznik, Maria Anna, Allen, Craig S.
• Granted Patent: US 6,819,540 B2
• Time in Patent Office: Days
• US Class Current: 361/306.3
• CPC Class Codes: H01G 4/06 Solid dielectrics
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 2201/0116 Porous, e.g. foam
• CPC Class Codes: H05K 2201/0195 Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
• CPC Class Codes: H05K 2201/0212 Resin particles
• CPC Class Codes: H05K 2201/0236 Plating catalyst as filler in insulating material catalytic ink H05K2203/0709
• CPC Class Codes: H05K 2201/0355 Metal foils
• CPC Class Codes: H05K 2203/0773 Dissolving the filler without dissolving the matrix material; Dissolving the matrix material without dissolving the filler
• CPC Class Codes: H05K 3/181 by electroless plating adhesives therefor H05K3/387
• CPC Class Codes: H05K 3/381 by special treatment of the substrate

Abstract

Dielectric structures particularly suitable for use in capacitors and having a textured surface are provided, together with methods of forming these structures. Such dielectric structures show increased adhesion of subsequently applied conductive layers.

Claims

1. A capacitor structure comprising a first conductive layer, a second conductive layer and a multilayer dielectric structure disposed between the first and second conductive layers, wherein the multilayer dielectric structure comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has a textured surface.

2. The capacitor structure of claim 1 wherein the first dielectric layer has a thickness of <

50% of the total thickness of the dielectric structure.

3. The capacitor structure of claim 1 wherein the least one of the first and second dielectric layers is selected from the group consisting of polymers, ceramics, metal oxides and combinations thereof.

4. The capacitor structure of claim 1 wherein the dielectric structure has a dielectric constant of ≧

7.

5. The capacitor structure of claim 1 wherein the first conductive layer is in intimate contact with the textured surface of the first dielectric layer.

6. A method of improving the adhesion of a deposited conductive layer to a dielectric structure comprising the steps of depositing on a dielectric layer a top dielectric layer comprising porogen, removing the porogen to provide a textured surface on the top dielectric layer, and plating an electrode on the surface of the top dielectric layer.

7. The method of claim 6 wherein the dielectric structure has a dielectric constant of ≧

7.

8. The method of claim 6 wherein the top dielectric layer is selected from the group consisting of polymers, ceramics, metal oxides and combinations thereof.

9. The method of claim 6 wherein the porogen is a cross-linked polymer particle.

10. The method of claim 9 wherein the porogen has a mean particle size of up to 1000 nm.

11. The method of claim 6 wherein the top dielectric layer has a thickness of <

50% of the total thickness of the dielectric structure.

12. The method of claim 6 wherein the top dielectric layer further comprises a plating dopant.

13. A printed circuit board comprising an embedded capacitance material, wherein the embedded capacitance material comprises a multilayer dielectric structure comprising a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has a textured surface.

14. The printed wiring board of claim 13 wherein a conductive layer is disposed on the textured surface of the first dielectric layer.

15. The printed wiring board of claim 13 wherein the first dielectric layer has a thickness of <

50% of the total thickness of the dielectric structure.

16. The printed wiring board of claim 13 wherein the first dielectric layer is selected from the group consisting of polymers, ceramics, metal oxides and combinations thereof.

17. The printed wiring board of claim 13 wherein the first dielectric layer further comprises a plating dopant.

18. A method of manufacturing a multilayer printed circuit board comprising the step of embedding a capacitance material in one or more layers of the multilayer printed circuit board, wherein the capacitance material comprises a multilayer dielectric structure comprising a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has a textured surface.

19. The method of claim 18 further comprising the step of disposing a conductive layer on the textured surface of the first dielectric layer.

20. The method of claim 18 wherein the first dielectric layer further comprises a plating dopant.