Timing calibration apparatus and method for a memory device signaling system

• US 20030131160A1
• Filed: 10/22/2002
• Published: 07/10/2003
• Est. Priority Date: 10/22/2001
• Status: Active Grant

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Perego, Richard E., Tsern, Ely K., Hampel, Craig E., Ware, Fredrick A., Sidiropoulos, Stefanos S.
• Granted Patent: US 6,920,540 B2
• Time in Patent Office: Days
• US Class Current: 710/22
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0671 In-line storage system
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4078 Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells protection of memory contents during checking or testing G11C29/52
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 21/00 Digital stores in which the information circulates continuouslystepwise G11C19/00
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H04L 67/10 in which an application is distributed across nodes in the network software deployment G06F8/60; multiprogramming arrangements G06F9/46
• CPC Class Codes: H04L 7/0025 : interpolation of clock signal
• CPC Class Codes: H04L 7/0079 : Receiver details
• CPC Class Codes: H04L 7/0091 : Transmitter details
• CPC Class Codes: H10B 43/27 : the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A memory system includes a memory controller and a memory component coupled to each other. An interface of the memory component is configured to receive a first signal from the memory controller with read request information, retrieve the read data information from the memory core in response to the request information, and transmit to the memory controller a second signal containing the read data information. The read data information includes read data symbols, where the average duration of the read data symbols, measured at the interface, defines a symbol time interval. A first external access time is measured at the interface between a first read request and read data transmitted by the interface in response to the first read request. A second external access time interval is measured at the interface between a second read request and read data transmitted by the interface in response to the second read request. The difference between the first external access time and the second external access time is greater than one-half of the symbol time interval.

Claims

1. A memory system, comprising:

a memory controller;

a memory component having a memory core for holding read data information and an interface that is coupled to at least one bus that is also coupled to the memory controller for conveying signals between the memory controller and the memory component;

the interface of the memory component configured to;

receive a first signal from the memory controller with read request information;

retrieve the read data information from the memory core in response to the request information; and

transmit to the memory controller a second signal containing the read data information, wherein the read data information is comprised of read data symbols and where the average duration of the read data symbols, measured at the interface, defines a symbol time interval, wherein the read request information includes a first read request and a second read request having an internal access time similar to an internal read access time of the first read request;

wherein operation of the memory component is characterized by;

a first external access time interval, measured at the interface, between the first read request and respective first read data transmitted by the interface in response to the first read request;

a second external access time interval, measured at the interface, between the second read request and respective second read data transmitted by the interface in response to the second read request; and

the difference between the first external access time and the second external access time is greater than one-half of the symbol time interval.

2. The system of claim 1, wherein the difference between the first access time and the second access time is greater than one symbol time interval.

3. The system of claim 1, wherein the operation of the memory component is further characterized by:

a third external access time interval, measured at the interface, between a third read request and respective third read data transmitted by the interface in response to the third read request;

the difference between the first external access time and the third external access time is less than one-half of the symbol time interval.

4. The system of claim 1, wherein

the interface of the memory component is further configured to receive timing signals from the memory controller, the timing signals carrying timing information indicating when the read request information is to be sampled and when the read data symbols are to be driven.

5. A memory system, comprising:

a memory controller;

a memory component having a memory core for holding read data information and an interface that is coupled to at least one bus that is also coupled to the memory controller for conveying signals between the memory controller and the memory component;

the interface of the memory component configured to;

receive a timing signal;

receive a first signal with read request information;

retrieve the read data information from the memory core in response to the request information; and

transmit a second signal containing the read data information, wherein the read data information is comprised of read data symbols and where the average duration of the read data symbols, measured at the interface, defines a symbol time interval, wherein the read request information includes a first read request and a second read request having an internal access time similar to an internal read access time of the first read request;

wherein operation of the memory component is characterized by;

a first external access time interval, measured at the interface, between a timing event on the timing signal that is associated with the first read request and respective first read data transmitted by the interface in response to the first read request;

a second external access time interval, measured at the interface, between a timing event on the timing signal that is associated with the second read request and respective second read data transmitted by the interface in response to the second read request; and

the difference between the first external access time and the second external access time is greater than one-half of the symbol time interval.

6. The system of claim 5, wherein the difference between the first access time and the second access time is greater than one symbol time interval.

7. The system of claim 5, wherein the operation of the memory component is further characterized by:

a third external access time interval, measured at the interface, between a third read request and respective third read data transmitted by the interface in response to the third read request;

the difference between the first external access time and the third external access time is less than one-half of the symbol time interval.

8. A memory system, comprising:

a memory controller;

a memory component having a memory core for holding read data information and an interface that is coupled to at least one bus that is also coupled to the memory controller for conveying signals between the memory controller and the memory component;

the interface of the memory component configured to;

receive a first signal with timing information;

retrieve the read data information from the memory core; and

transmit a second signal containing the read data information, wherein the read data information is comprised of read data symbols and where the average duration of the read data symbols, measured at the interface, defines a symbol time interval;

wherein operation of the memory component is characterized by;

a first drive offset time interval, measured at the interface, between a first timing event on the timing signal and a respective first read data symbol transmitted by the interface, the first timing event associated with the first read data symbol;

a second drive offset time interval, measured at the interface, between a second timing event on the timing signal and a respective second read data symbol transmitted by the interface, the second timing event associated with the second read data symbol; and

the difference between the first drive offset time and the second drive offset time is greater than one-half of the symbol time interval.

9. A system, comprising:

a first component;

a second component, the second component including storage for holding data information and an interface that is coupled to at least one bus that is also coupled to the first component for conveying signals between the first component and the second component;

the interface of the second component configured to;

receive a timing signal;

retrieve the data information from the storage; and

transmit a second signal containing the data information, wherein the data information is comprised of data symbols and where the average duration of the data symbols, measured at the interface, defines a symbol time interval;

wherein operation of the second component is characterized by;

a first drive offset time interval, measured at the interface, between a first timing event on the timing signal and a respective first data symbol transmitted by the interface, the first timing event associated with the first data symbol;

a second drive offset time interval, measured at the interface, between a second timing event on the timing signal and a respective second read data symbol transmitted by the interface, the second timing event associated with the second data symbol; and

the difference between the first drive offset time and the second drive offset time is greater than one-half of the symbol time interval.

10. The system of claim 9 where the second component includes an internal module configured to perform functions other than memory functions.

11. A device comprising a single integrated circuit having a plurality of internal modules, the device comprising:

a first module; and

a second module having storage for holding data information and an interface that is coupled to at least one bus that is also coupled to the first module for conveying signals between the first module and the second module;

the interface of the second module configured to;

receive a first signal with timing information;

retrieve the data information from the storage; and

transmit a second signal containing the data information, wherein the data information is comprised of data symbols and where the average duration of the data symbols, measured at the interface, defines a symbol time interval;

wherein operation of the component is characterized by;

a first drive offset time interval, measured at the interface, between a first timing event on the timing signal and a respective first data symbol transmitted by the interface, the first timing event associated with the first data symbol;

a second drive offset time interval, measured at the interface, between a second timing event on the timing signal and a respective second data symbol transmitted by the interface, the second timing event associated with the second data symbol; and

the difference between the first drive offset time and the second drive offset time is greater than one-half of the symbol time interval.

14. The memory component of claim 11, wherein

the interface of the memory component is further configured to receive timing signals, the timing signals carrying timing information indicating when the read request information is to be sampled and when the read data symbols are to be driven.

12. A memory component comprising:

a memory core for holding read data information; and

an interface configured to;

receive a first signal with read request information;

retrieve the read data information from the memory core in response to the request information; and

transmit a second signal containing the read data information, wherein the read data information is comprised of read data symbols and where the average duration of the read data symbols, measured at the interface, defines a symbol time interval, wherein the read request information includes a first read request and a second read request having an internal access time similar to an internal read access time of the first read request;

wherein operation of the memory component is characterized by;

a first external access time interval, measured at the interface, between the first read request and respective first read data transmitted by the interface in response to the first read request;

a second external access time interval, measured at the interface, between the second read request and respective second read data transmitted by the interface in response to the second read request; and

the difference between the first external access time and the second external access time is greater than one-half of the symbol time interval.

13. The memory component of claim 12, wherein the difference between the first external access time and the second external access time is greater than one symbol time interval.

15. A memory component comprising:

a memory core for holding read data information; and

an interface configured to;

receive a timing signal;

receive a first signal with read request information;

retrieve the read data information from the memory core in response to the request information; and

transmit a second signal containing the read data information, wherein the read data information is comprised of read data symbols and where the average duration of the read data symbols, measured at the interface, defines a symbol time interval, wherein the read request information includes a first read request and a second read request having an internal access time similar to an internal read access time of the first read request;

wherein operation of the memory component is characterized by;

a first external access time interval, measured at the interface, between a timing event on the timing signal that is associated with the first read request and respective first read data transmitted by the interface in response to the first read request;

a second external access time interval, measured at the interface, between a timing event on the timing signal that is associated with the second read request and respective second read data transmitted by the interface in response to the second read request; and

the difference between the first external access time and the second external access time is greater than one-half of the symbol time interval.

16. The memory component of claim 15, wherein the difference between the first external access time and the second external access time is greater than one symbol time interval.

17. A memory component comprising:

a memory core for holding read data information; and

an interface configured to;

receive a timing signal;

retrieve the read data information from the memory core; and

transmit a second signal containing the read data information, wherein the read data information is comprised of read data symbols and where the average duration of the read data symbols, measured at the interface, defines a symbol time interval;

wherein operation of the memory component is characterized by;

a first drive offset time interval, measured at the interface, between a first timing event on the timing signal and a respective first read data symbol transmitted by the interface, the first timing event associated with the first read data symbol;

a second drive offset time interval, measured at the interface, between a second timing event on the timing signal and respective second read data symbol transmitted by the interface, the second timing event associated with the second read data symbol; and

the difference between the first drive offset time and the second drive offset time is greater than one-half of the symbol time interval.

18. A device comprising a single integrated circuit having a plurality of modules, the device comprising:

a non-memory module;

storage for holding data information; and

an interface configured to;

receive a timing signal;

retrieve the data information from the storage; and

transmit a second signal containing the data information, wherein the data information is comprised of data symbols and where the average duration of the data symbols, measured at the interface, defines a symbol time interval;

wherein operation of the electronic device is characterized by;

a first drive offset time interval, measured at the interface, between a first timing event on the timing signal and respective first data symbol transmitted by the interface, the first timing event associated with the first data symbol;

a second drive offset time interval, measured at the interface, between a second timing event on the timing signal and respective second read data symbol transmitted by the interface, the second timing event associated with the second data symbol; and

the difference between the first drive offset time and the second drive offset time is greater than one-quarter of the symbol time interval.

19. A memory system, comprising:

a memory controller;

a memory component having a memory core for holding data and an interface that is coupled to at least one bus that is also coupled to the memory controller for conveying signals between the memory controller and the memory component;

the interface of the memory component configured to;

receive a timing signal;

receive a first signal from the memory controller with write request information;

receive a second signal from the memory controller with write data information;

store the write data information in the memory core in response to the write request information; and

wherein the write data information is comprised of data symbols and where the average duration of the data symbols, measured at the interface, defines a symbol time interval, wherein the write request information includes a first write request and a second write request having an internal access time similar to an internal write access time of the first write request;

wherein operation of the memory component is characterized by;

a first external access time interval, measured at the interface of the memory component, between the first write request and a respective first write data symbol received by the memory component in conjunction with the first write request;

a second external access time interval, measured at the interface of the memory component, between the second write request and a respective second write data symbol received by the memory component in conjunction with the second write request; and

the difference between the first external access time interval and the second external access time interval is greater than one-half of the symbol time interval.

20. The system of claim 19, wherein the difference between the first external access time and the second external access time is greater than one symbol time interval.

21. The system of claim 19, wherein

the interface of the memory component is further configured to receive timing signals from the memory controller, the timing signals carrying timing information indicating when the write request information is to be sampled and when the write data symbols are to be sampled.

22. A memory system, comprising:

a memory controller;

a memory component having a memory core for holding data and an interface that is coupled to at least one bus that is also coupled to the memory controller for conveying signals between the memory controller and the memory component;

the interface of the memory component configured to;

receive a first signal from the memory controller with write request information;

receive a second signal from the memory controller with write data information;

store the write data information in the memory core in response to the write request information; and

wherein the write data information is comprised of data symbols and where the average duration of the data symbols, measured at the interface, defines a symbol time interval, wherein the write request information includes a first write request and a second write request having an internal access time similar to an internal write access time of the first write request;

wherein operation of the memory component is characterized by;

a first external access time interval, measured at the interface of the memory component, between a first timing event on the timing signal and a respective first write data symbol received by the memory component in conjunction with the first write request, the first timing event associated with the first write request;

a second external access time interval, measured at the interface of the memory component, between a second timing event on the timing signal and a respective second write data symbol received by the memory component in conjunction with the second write request, the second timing event associated with the second write request; and

the difference between the first external access time interval and the second external access time interval is greater than one-half of the symbol time interval.

23. The system of claim 22, wherein the difference between the first external access time interval and the second external access time interval is greater than one symbol time interval.

24. A memory system, comprising:

a memory controller;

a memory component having a memory core for holding data and an interface that is coupled to at least one bus that is also coupled to the memory controller for conveying signals between the memory controller and the memory component;

the interface of the memory component configured to;

receive a timing signal;

receive a first signal from the memory controller with write request information;

receive a second signal from the memory controller with write data information;

store the write data information in the memory core in response to the write request information; and

wherein the write data information is comprised of data symbols and where the average duration of the data symbols, measured at the interface, defines a symbol time interval, wherein the write request information includes a first write request and a second write request having an internal access time similar to an internal write access time of the first write request;

wherein operation of the memory component is characterized by;

a first offset time interval, measured at the interface, between a first timing event on the timing signal and a respective first write data symbol received by the interface, the first timing event associated with the first write data symbol;

a second offset time interval, measured at the interface, between a second timing event on the timing signal and a respective second write data symbol received by the interface, the second timing event associated with the second write data symbol; and

the difference between the first offset time and the second offset time is greater than one-half of the symbol time interval.

25. A system, comprising:

a first component;

a second component, the second component including storage for holding data and an interface that is coupled to at least one bus that is also coupled to the first component for conveying signals between the first component and the second component;

the interface of the second component configured to;

receive a timing signal;

receive a second signal from the first component with write data information;

store the write data information in the storage; and

wherein the write data information is comprised of data symbols and where the average duration of the data symbols, measured at the interface, defines a symbol time interval;

wherein operation of the second component is characterized by;

a first offset time interval, measured at the interface, between a first timing event on the timing signal and a respective first write data symbol received by the interface, the first timing event associated with the first write data symbol;

a second offset time interval, measured at the interface, between a second timing event on the timing signal and a respective second write data symbol received by the interface, the second timing event associated with the second write data symbol; and

the difference between the first offset time and the second offset time is greater than one-half of the symbol time interval.

26. A device comprising a single integrated circuit having a plurality of modules, the device comprising:

a first module comprising a controller; and

a second module having a memory core for holding data and an interface that is coupled to at least one bus that is also coupled to the memory controller for conveying signals between the memory controller and the memory component;

the interface of the second module configured to;

receive a timing signal;

receive a first signal from the controller with write request information;

receive a second signal from the controller with write data information;

store the write data information in the memory core in response to the write request information; and

wherein the write data information is comprised of data symbols and where the average duration of the data symbols, measured at the interface, defines a symbol time interval, wherein the write request information includes a first write request and a second write request having an internal access time similar to an internal write access time of the first write request;

wherein operation of the memory component is characterized by;

a first offset time interval, measured at the interface, between a first timing event on the timing signal and a respective first write data symbol received by the interface, the first timing event associated with the first write data symbol;

a second offset time interval, measured at the interface, between a second timing event on the timing signal and a respective second write data symbol received by the interface, the second timing event associated with the second write data symbol; and

the difference between the first offset time and the second offset time is greater than one-half of the symbol time interval.

27. A memory component comprising:

a memory core for holding data;

an interface configured to;

receive a first signal with write request information;

receive a second signal with write data information;

store the write data information in the memory core in response to the write request information; and

wherein the write data information is comprised of data symbols and where the average duration of the data symbols, measured at the interface, defines a symbol time interval, wherein the write request information includes a first write request and a second write request having an internal access time similar to an internal write access time of the first write request;

wherein operation of the memory component is characterized by;

a first external access time interval, measured at the interface of the memory component, between the first write request and a respective first write data symbol received by the memory component in conjunction with the first write request;

a second external access time interval, measured at the interface of the memory component, between the second write request and a respective first write data symbol received by the memory component in conjunction with the second write request; and

the difference between the first external access time and the second external access time is greater than one-half of the symbol time interval.

28. The memory component of claim 27, wherein the difference between the first access time and the second access time is greater than one symbol time interval.

29. The memory component of claim 27, wherein

the interface of the memory component is further configured to receive timing signals, the timing signals carrying timing information indicating when the write request information is to be sampled and when the write data symbols are to be sampled.

30. A memory component comprising:

a memory core for holding data;

an interface configured to;

receive a timing signal;

receive a first signal with write request information;

receive a second signal with write data information;

store the write data information in the memory core in response to the write request information; and

wherein the write data information is comprised of data symbols and where the average duration of the data symbols, measured at the interface, defines a symbol time interval, wherein the write request information includes a first write request and a second write request having an internal access time similar to an internal write access time of the first write request;

wherein operation of the memory component is characterized by;

a first external access time interval, measured at the interface of the memory component, between a first timing event on the timing signal and a respective first write data symbol received by the memory component in conjunction with the first write request, the first timing event associated with the first write request;

a second external access time interval, measured at the interface of the memory component, between a second timing event on the timing signal and a respective second write data symbol received by the memory component in conjunction with the second write request, the second timing event associated with the second write request; and

the difference between the first external access time and the second external access time is greater than one-half of the symbol time interval.

31. The memory component of claim 30, wherein the difference between the first external access time and the second external access time is greater than one symbol time interval.

32. A memory component, comprising:

a memory core for holding data and an interface that is coupled to at least one bus that is also coupled to the memory controller for conveying signals between the memory controller and the memory component;

the interface of the memory component configured to;

receive a timing signal;

receive a second signal with write data information to be stored in the memory core; and

store the write data information in the memory core;

wherein the write data information is comprised of write data symbols and where the average duration of the write data symbols, measured at the interface, defines a symbol time interval;

wherein operation of the memory component is characterized by;

a first offset time interval, measured at the interface, between a first timing event on the timing signal and a respective first write data symbol received by the interface, the first timing event associated with the first write data symbol;

a second offset time interval, measured at the interface, between a second timing event on the timing signal and a respective second write data symbol received by the interface, the second timing event associated with the second write data symbol; and

the difference between the first offset time and the second offset time is greater than one-half of the symbol time interval.

33. A device comprising a single integrated circuit having a plurality of modules, the device comprising:

storage for holding data;

an interface coupled to the storage, the interface configured to;

receive a timing signal;

receive a second signal with write data information; and

store the write data information in the storage;

wherein the write data information is comprised of write data symbols and where the average duration of the write data symbols, measured at the interface, defines a symbol time interval;

wherein operation of the second component is characterized by;

a first offset time interval, measured at the interface, between a first timing event on the timing signal and a respective first write data symbol received by the interface, the first timing event associated with the first write data symbol;

a second offset time interval, measured at the interface, between a second timing event on the timing signal and a respective second write data symbol received by the interface, the second timing event associated with the second write data symbol; and

the difference between the first offset time and the second offset time is greater than one-half of the symbol time interval.

34. A memory system, comprising:

a memory controller;

a first memory component having an interface coupled to the memory controller, the interface configured to receive respective read data symbols from the first memory component, where average duration of the respective read data symbols, measured at the interface of the first memory component, defines a symbol time interval;

the interface of the first memory component also configured to receive from the memory controller respective request signals, including a first read request; and

a second memory component having an interface coupled to the memory controller, the interface configured to receive second read data symbols from the second memory component;

the interface of the second memory component also configured to receive from the memory controller respective request signals, including a second read request;

a first external access time interval, measured at the interface of the first memory component, between the first read request and a respective first read data symbol retrieved by the first memory component in response to the first read request;

a second external access time interval, measured at the interface of the second memory component, between the second read request and a respective second read data symbol retrieved by the second memory component in response to the second read request; and

wherein the first and second memory components are coupled to the memory controller by different data buses and by a common request bus that conveys the respective request signals, and the difference between the first external access time and the second external access time is greater than one-half of the symbol time interval.

35. The system of claim 34, wherein the difference between the first external access time and the second external access time is greater than one symbol time interval.

36. The system of claim 34, wherein

the interface of the first memory component and the interface of the second memory component are each further configured to receive timing signals from the memory controller, the timing signals carrying timing information indicating when the read request information is to be sampled and when the read data symbols are to be driven.

37. A memory system, comprising:

a memory controller;

a first memory component having an interface coupled to the memory controller, the interface configured to receive respective read data symbols from the first memory component, where average duration of the respective read data symbols, measured at the interface of the first memory component, defines a symbol time interval;

the interface of the first memory component also configured to receive from the memory controller a timing signal and respective request signals, the request signals including a first read request; and

a second memory component having an interface coupled to the memory controller, the interface configured to receive second read data symbols from the second memory component;

the interface of the second memory component also configured to receive from the memory controller the timing signal and respective request signals, including a second read request;

a first external access time interval, measured at the interface of the first memory component, between a first timing event on the timing signal and a respective first read data symbol retrieved by the first memory component in response to the first read request, the first timing event associated with the first read request;

a second external access time interval, measured at the interface of the second memory component, between the first timing event on the timing signal and a respective second read data symbol retrieved by the second memory component in response to the first read request, the second timing event associated with the first read request; and

wherein the first and second memory components are coupled to the memory controller by different data buses and by a common request bus that conveys the respective request signals, and the difference between the first external access time interval and the second external access time interval is greater than one-half of the symbol time interval.

38. The memory system of claim 37, wherein the difference between the first external access time interval and the second external access time interval is greater than one symbol time interval.

39. A memory system, comprising:

a memory controller;

a first memory component having an interface coupled to the memory controller, the interface configured to receive respective write data symbols from the memory controller, where average duration of the respective write data symbols, measured at the interface of the first memory component, defines a symbol time interval;

the interface of the first memory component also configured to receive from the memory controller respective write request signals, including a first write request; and

a second memory component having an interface that is coupled to the memory controller, the interface of the second memory component configured to receive respective write data symbols from the memory controller;

the interface of the second memory component also configured to receive from the memory controller respective write request signals, including a second write request; and

a first external access time, measured at the interface of the first memory component, between the first write request and a respective first write data symbol received by the first memory component in conjunction with the first write request;

a second external access time, measured at the interface of the second memory component, between the first write request and a respective second write data symbol retrieved by the second memory component in response to the first write request; and

the difference between the first external access time and the second external access time is greater than one-half of the symbol time interval.

40. The memory system of claim 39, wherein the difference between the first external access time and the second external access time is greater than one symbol time interval.

41. The memory system of claim 39, wherein

the interface of the first memory component and the interface of the second memory component are each further configured to receive timing signals from the memory controller, the timing signals carrying timing information indicating when the write request information is to be sampled and when the write data symbols are to be sampled.

42. A memory system, comprising:

a memory controller;

a first memory component having an interface coupled to the memory controller, the interface configured to receive respective write data symbols from the memory controller, where average duration of the respective write data symbols, measured at the interface of the first memory component, defines a symbol time interval;

the interface of the first memory component also configured to receive from the memory controller respective timing signal and write request signals, including a first write request; and

a second memory component having an interface that is coupled to the memory controller, the interface of the second memory component configured to receive respective write data symbols from the memory controller;

the interface of the second memory component also configured to receive from the memory controller the timing signals and respective write request signals, including a second write request; and

a first external access time, measured at the interface of the first memory component, between a first timing event on the timing signal and a respective first write data symbol received by the first memory component in conjunction with the first write request, the first timing event associated with the first write request;

a second external access time, measured at the interface of the second memory component, between the first timing event on the timing signal and a respective second write data symbol retrieved by the second memory component in response to the second write request; and

the difference between the first external access time and the second external access time is greater than one-half of the symbol time interval.

43. The memory system of claim 42, wherein the difference between the first external access time and the second external access time is greater than one of the symbol time interval.

44. A memory controller comprising:

an interface configured to receive symbols of information by sampling a first signal at a determined timing offset relative to a reference clock signal;

wherein the determined timing offset initially has a first timing offset value and wherein average duration of the symbols, measured at the interface of the memory controller, defines a symbol time interval; and

calibration apparatus configured to iteratively determine suitability of the determined timing offset and adjust the determined timing offset to have an updated timing offset value;

wherein the updated timing offset value after multiple calibration iterations is a second timing offset value; and

wherein the difference between the first timing offset value and the second timing offset value is greater than one-half of the symbol time interval.

45. The memory controller of claim 44, wherein the difference between the first timing offset and the second timing offset is greater than the symbol time interval.

46. The memory controller of claim 44, wherein the calibration apparatus includes a first register for a current value of the determined timing offset.

47. The memory controller of claim 44, wherein the calibration apparatus is configured to send calibration information to a memory component and to then receive it back from the memory component in order to measure the suitability of the determined timing offset.

48. The memory controller of claim 44, wherein the calibration apparatus is configured to periodically perform the suitability determination and timing offset adjustment between intervals of normal memory system operation.

49. The memory controller of claim 44, wherein the calibration apparatus is configured to determine suitability of the determined timing offset by measuring the suitability of a first margin timing offset and by measuring the suitability of a second margin timing offset.

50. The memory controller of claim 49, wherein the first margin timing offset is stored in a first margin register and the second margin timing offset is stored in a second margin register and the calibration apparatus is configured to adjust the first margin timing offset to make it more suitable for sampling the first signal.

51. The memory controller of claim 49, wherein the calibration apparatus configured to combine the first margin timing offset and the second margin timing offset to generate the updated timing offset.

52. A controller comprising:

an interface configured to receive symbols of information by sampling a first signal at a determined timing offset relative to a reference clock signal;

wherein the determined timing offset initially has a first timing offset value and wherein average duration of the symbols, measured at the interface of the controller, defines a symbol time interval; and

calibration apparatus configured to iteratively determine suitability of the determined timing offset and adjust the determined timing offset to have an updated timing offset value;

wherein the updated timing offset value after multiple calibration iterations is a second timing offset value; and

wherein the difference between the first timing offset value and the second timing offset value is greater than one-half of the symbol time interval.

53. A memory system, comprising:

a memory controller;

a memory component having a memory core for holding data information and an interface that is coupled to at least one bus that is also coupled to the memory controller for conveying signals between the memory controller and the memory component;

the memory controller comprising;

an interface configured to receive symbols of information by sampling a first signal at a determined timing offset relative to a reference clock signal;

wherein the determined timing offset initially has a first timing offset value and wherein average duration of the symbols, measured at the interface of the memory controller, defines a symbol time interval; and

calibration apparatus configured to iteratively determine suitability of the determined timing offset and adjust the determined timing offset to have an updated timing offset value;

wherein the updated timing offset value after multiple calibration iterations is a second timing offset value; and

wherein the difference between the first timing offset value and the second timing offset value is greater than one-half of the symbol time interval.

54. A system, comprising:

a first component;

a second component, the second component including storage for holding data information and an interface that is coupled to at least one bus that is also coupled to the first component;

the first component including;

an interface configured to receive symbols of information by sampling a first signal at a determined timing offset relative to a reference clock signal;

wherein the determined timing offset initially has a first timing offset value and wherein average duration of the symbols, measured at the interface of the first component, defines a symbol time interval; and

calibration apparatus configured to iteratively determine suitability of the determined timing offset and adjust the determined timing offset to have an updated timing offset value;

wherein the updated timing offset value after multiple calibration iterations is a second timing offset value; and

wherein the difference between the first timing offset value and the second timing offset value is greater than one-half of the symbol time interval.

55. A device comprising a single integrated circuit having a plurality of internal modules, the device comprising:

a first module; and

a second module having storage for holding data information and an interface that is coupled to at least one bus that is also coupled to the first module for conveying signals between the first module and the second module;

the first module including;

an interface configured to receive symbols of information by sampling a first signal at a determined timing offset relative to a reference clock signal;

wherein the determined timing offset initially has a first timing offset value and wherein average duration of the symbols, measured at the interface of the first module, defines a symbol time interval; and

calibration apparatus configured to iteratively determine suitability of the determined timing offset and adjust the determined timing offset to have an updated timing offset value;

wherein the updated timing offset value after multiple calibration iterations is a second timing offset value; and

wherein the difference between the first timing offset value and the second timing offset value is greater than one-half of the symbol time interval.

56. A memory controller for use in conjunction with a memory component coupled to at least one bus for conveying signals between the memory component and the memory controller, the memory controller comprising:

an interface that is coupled to the at least one bus and that is configured to transmit data symbols to the memory component by driving a first signal on the at least one bus at a determined timing offset relative to a reference clock signal;

wherein the determined timing offset is initially a first timing offset and wherein average duration of the data symbols, measured at the interface of the memory controller, defines a symbol time interval; and

calibration apparatus configured to iteratively determine suitability of the determined timing offset and adjust the determined timing offset to an updated timing offset;

wherein the updated timing offset value after multiple calibration iterations is a second timing offset value; and

wherein the difference between the first timing offset value and the second timing offset value is greater than one-half of the symbol time interval.

57. The memory controller of claim 56, wherein the difference between the first timing offset and the second timing offset is greater than the symbol time interval.

58. The memory controller of claim 56, wherein the calibration apparatus includes a first register for a current value of the determined timing offset.

59. The memory controller of claim 56, wherein the calibration apparatus is configured to send calibration information to the memory component and to then receive it back from the memory component in order to measure the suitability of the determined timing offset.

60. The memory controller of claim 56, wherein the calibration apparatus is configured to periodically perform the suitability determination and timing offset adjustment between intervals of normal memory system operation.

61. The memory controller of claim 56, wherein the calibration apparatus is configured to determine suitability of the determined timing offset by measuring the suitability of a first margin timing offset and by measuring the suitability of a second margin timing offset.

62. The memory controller of claim 61, wherein the first margin timing offset is stored in a first margin register and the second margin timing offset is stored in a second margin register and the calibration apparatus is configured to adjust the first margin timing offset to make it more suitable for sampling the first signal.

63. The memory controller of claim 61, wherein the calibration apparatus configured to combine the first margin timing offset and the second margin timing offset to generate the updated timing offset.

64. A controller for use in conjunction with a device coupled to at least one bus for conveying signals between the component and the device, the controller comprising:

an interface that is coupled to the at least one bus and that is configured to transmit data symbols to the memory component by driving a first signal on the at least one bus at a determined timing offset relative to a reference clock signal;

wherein the determined timing offset is initially a first timing offset and wherein average duration of the data symbols, measured at the interface of the controller, defines a symbol time interval; and

calibration apparatus configured to iteratively determine suitability of the determined timing offset and adjust the determined timing offset to an updated timing offset;

wherein the updated timing offset value after multiple calibration iterations is a second timing offset value; and

wherein the difference between the first timing offset value and the second timing offset value is greater than one-half of the symbol time interval.

65. A memory system, comprising:

a memory controller;

a memory component for use in conjunction with the memory controller coupled to at least one bus for conveying signals between the memory component and the memory controller;

the memory controller comprising;

an interface that is coupled to the at least one bus and that is configured to transmit data symbols to the memory component by driving a first signal on the at least one bus at a determined timing offset relative to a reference clock signal;

wherein the determined timing offset is initially a first timing offset and wherein average duration of the data symbols, measured at the interface of the memory controller, defines a symbol time interval; and

calibration apparatus configured to iteratively determine suitability of the determined timing offset and adjust the determined timing offset to an updated timing offset;

wherein the updated timing offset value after multiple calibration iterations is a second timing offset value; and

wherein the difference between the first timing offset value and the second timing offset value is greater than one-half of the symbol time interval.

66. A system, comprising:

a first component;

a second component, the second component including storage for holding data information and an interface that is coupled to at least one bus that is also coupled to the first component;

the first component including;

an interface that is coupled to the at least one bus and that is configured to transmit data symbols to the memory component by driving a first signal on the at least one bus at a determined timing offset relative to a reference clock signal;

wherein the determined timing offset is initially a first timing offset and wherein average duration of the data symbols, measured at the interface of the first component, defines a symbol time interval; and

calibration apparatus configured to iteratively determine suitability of the determined timing offset and adjust the determined timing offset to an updated timing offset;

wherein the updated timing offset value after multiple calibration iterations is a second timing offset value; and

wherein the difference between the first timing offset value and the second timing offset value is greater than one-half of the symbol time interval.

67. A device comprising a single integrated circuit having a plurality of internal modules, the device comprising:

a first module; and

a second module having storage for holding data information and an interface that is coupled to at least one bus that is also coupled to the first module for conveying signals between the first module and the second module;

the first module comprising;

an interface that is coupled to the at least one bus and that is configured to transmit data symbols to the memory component by driving a first signal on the at least one bus at a determined timing offset relative to a reference clock signal;

wherein the determined timing offset is initially a first timing offset and wherein average duration of the data symbols, measured at the interface of the first module, defines a symbol time interval; and

calibration apparatus configured to iteratively determine suitability of the determined timing offset and adjust the determined timing offset to an updated timing offset;

wherein the updated timing offset value after multiple calibration iterations is a second timing offset value; and

wherein the difference between the first timing offset value and the second timing offset value is greater than one-half of the symbol time interval.

68. A memory component, comprising:

an interface configured to receive a first signal comprising a symbol and a second signal comprising timing information, wherein the timing information includes a plurality of timing events associated with the symbol; and

calibration apparatus configured to determine suitability of the plurality of timing events and to select, based on the suitability determination, one of the plurality of timing events for use as a sampling point for sampling the symbol.

69. The memory component of claim 68, wherein the calibration apparatus is configured to periodically perform the suitability determination and timing event selection between intervals of normal memory system operation.

70. The memory component of claim 68, wherein the symbol is a first symbol and the first signal comprises a plurality of symbols that includes the first symbol, and wherein the timing information includes a plurality of timing events associated with each symbol of the plurality of symbols, and the calibration apparatus is configured to select the same one of the plurality of timing events associated with each symbol to use as a sampling point for sampling each symbol.

71. A memory system, comprising:

a first memory component having a first interface configured to receive a first signal comprising a symbol and a second signal comprising timing information, wherein the timing information includes a plurality of timing events associated with the symbol; and

having a first calibration apparatus configured to determine suitability of the plurality of timing events and to select, based on the suitability determination, one of the plurality of timing events for use as a sampling point for sampling the symbol; and

a second memory component having a second interface configured to receive the first signal comprising the first symbol and the second signal comprising the timing information; and

having a second calibration apparatus configured to determine suitability of the plurality of timing events and to select, based on the suitability determination, another one of the plurality of timing events for use as a sampling point for sampling the symbol;

wherein the first selected timing event is selected by the first calibration apparatus independently of the selection of the second selected timing event by the second calibration apparatus.

72. The memory system of claim 71, wherein the first selected timing event and the second selected timing event are different ones of the plurality of timing events.

73. The memory system of claim 71, wherein the symbol is a first symbol and the first signal comprises a plurality of symbols that includes the first symbol, and wherein the timing information includes a plurality of timing events associated with each symbol of the plurality of symbols, and the calibration apparatus is configured to select the same one of the plurality of timing events associated with each symbol to use as a sampling point for sampling each symbol.

74. A memory component, comprising:

an interface configured to drive a first signal comprising a symbol and to receive a second signal comprising timing information, wherein the timing information includes a plurality of timing events associated with the symbol; and

calibration apparatus configured to determine suitability of the plurality of timing events and to select, based on the suitability determination, one of the plurality of timing events for use as a driving point for driving the symbol onto the first signal.

75. The memory component of claim 74, wherein the calibration apparatus is configured to periodically perform the suitability determination and timing event selection between intervals of normal memory system operation.

76. The memory component of claim 74, wherein the symbol is a first symbol and the first signal comprises a plurality of symbols that includes the first symbol, and wherein the timing information includes a plurality of timing events associated with each symbol of the plurality of symbols, and the calibration apparatus is configured to select the same one of the plurality of timing events associated with each symbol to use as a sampling point for sampling each symbol.

77. A memory system, comprising:

a first memory component having a first interface configured to drive a first signal comprising a respective symbol and to receive a second signal comprising timing information, wherein the timing information includes a plurality of timing events associated with the respective symbol; and

having a first calibration apparatus configured to determine suitability of the plurality of timing events and to select, based on the suitability determination, a first one of the plurality of timing events for use as a driving point for driving the respective symbol; and

a second memory component having a second interface configured to driving a third signal comprising a respective symbol and to receive the second signal comprising the timing information; and

having a second calibration apparatus configured to determine suitability of the plurality of timing events and to select, based on the suitability determination, a second one of the plurality of timing events for use as a driving point for driving the respective symbol onto the third signal;

wherein the first selected timing event is selected by the first calibration apparatus independently of the selection of the second selected timing event by the second calibration apparatus.

78. The memory system of claim 77, wherein the first selected timing event and the second selected timing event are different ones of the plurality of timing events.

79. The memory system of claim 77, wherein the first signal comprises a plurality of symbols, and wherein the timing information includes a plurality of timing events associated with each symbol of the plurality of symbols, and the first calibration apparatus is configured to select the same one of the plurality of timing events associated with each symbol to use as a driving point for driving each symbol of the plurality of symbols.

80. A memory controller comprising:

a first circuit configured to receive a first symbol by sampling the first signal using a first timing signal having a first timing offset relative to a reference clock signal, and to drive a second signal comprising the received first symbol; and

a second circuit configured to sample the received first symbol of the second signal using a second timing signal having a second timing offset relative to the reference clock signal;

wherein the first circuit and second circuit are configured to accommodate all possible differences between the first timing offset and the second timing offset that falls within a range extending between a first value through a second value, wherein the second value equals the first value plus one clock cycle of the reference clock signal.

81. The memory controller of claim 80, including a first register configured to store the first timing offset.

82. The memory controller of claim 80, including calibration apparatus configured to determine suitability of the first timing offset and adjust the first timing offset to make it more suitable for sampling the first signal.

83. The memory controller of claim 82, wherein the calibration apparatus is configured to periodically perform the suitability determination and adjusting the first timing offset between intervals in which normal memory read operations and memory write operations are performed.

84. The memory controller of claim 82, wherein the calibration apparatus is configured to send calibration information to the memory component and to then receive it back from the memory component in order to measure the suitability of the first timing offset.

85. The memory controller of claim 82, wherein the calibration apparatus is configured to determine suitability of the first timing offset by measuring the suitability of a first margin timing offset and by measuring the suitability of a second margin timing offset.

86. The memory controller of claim 85, wherein the first margin timing offset is stored in a first margin register and the second margin timing offset is stored in a second margin register and the calibration apparatus is configured to adjust the first margin timing offset to make it more suitable for sampling the first signal.

87. The memory controller of claim 85, wherein the calibration apparatus is configured to combine the first margin timing offset and the second margin timing offset to generate the first timing offset.

88. A memory controller comprising:

a first circuit configured to receive a first symbol by sampling the first signal using a first timing signal having a first timing offset relative to a reference clock signal, and to drive a second signal comprising the received first symbol; and

a second circuit configured to sample the received first symbol of the second signal using a second timing signal having a second timing offset relative to the reference clock signal;

wherein the first circuit and second circuit are configured to accommodate all possible differences between the first timing offset and the second timing offset that falls within a range extending between a first value through a second value, wherein the second value equals the first value plus two clock cycles of the reference clock signal.

89. A controller comprising:

a first circuit configured to receive a first symbol by sampling the first signal using a first timing signal having a first timing offset relative to a reference clock signal, and to drive a second signal comprising the received first symbol; and

a second circuit configured to sample the received first symbol of the second signal using a second timing signal having a second timing offset relative to the reference clock signal;

wherein the first circuit and second circuit are configured to accommodate all possible differences between the first timing offset and the second timing offset that falls within a range extending between a first value through a second value, wherein the second value equals the first value plus one clock cycle of the reference clock signal.

90. The controller of claim 89, including calibration apparatus configured to determine suitability of the first timing offset and adjust the first timing offset to make it more suitable for sampling the first signal.

91. A memory system, comprising:

a memory controller;

a memory component having a memory core for holding read data information and an interface that is coupled to at least one bus that is also coupled to the memory controller for conveying signals between the memory controller and the memory component;

the memory controller comprising;

a first circuit configured to receive a first symbol by sampling the first signal using a first timing signal having a first timing offset relative to a reference clock signal, and to drive a second signal comprising the received first symbol; and

a second circuit configured to sample the received first symbol of the second signal using a second timing signal having a second timing offset relative to the reference clock signal;

wherein the first circuit and second circuit are configured to accommodate all possible differences between the first timing offset and the second timing offset that falls within a range extending between a first value through a second value, wherein the second value equals the first value plus one clock cycle of the reference clock signal.

92. The memory system of claim 91, the memory controller including calibration apparatus configured to determine suitability of the first timing offset and adjust the first timing offset to make it more suitable for sampling the first signal.

93. A system, comprising:

a first component;

a second component, the second component including storage for holding data information and an interface that is coupled to at least one bus that is also coupled to the first component;

the first component including;

a first circuit configured to receive a first symbol by sampling the first signal using a first timing signal having a first timing offset relative to a reference clock signal, and to drive a second signal comprising the received first symbol; and

a second circuit configured to sample the received first symbol of the second signal using a second timing signal having a second timing offset relative to the reference clock signal;

wherein the first circuit and second circuit are configured to accommodate all possible differences between the first timing offset and the second timing offset that falls within a range extending between a first value through a second value, wherein the second value equals the first value plus one clock cycle of the reference clock signal.

94. The system of claim 93, the first component including calibration apparatus configured to determine suitability of the first timing offset and adjust the first timing offset to make it more suitable for sampling the first signal.

95. A device comprising a single integrated circuit having a plurality of internal modules, the device comprising:

a first module; and

a second module having storage for holding data information and an interface that is coupled to at least one bus that is also coupled to the first module for conveying signals between the first module and the second module;

the first module comprising;

a first circuit configured to receive a first symbol by sampling the first signal using a first timing signal having a first timing offset relative to a reference clock signal, and to drive a second signal comprising the received first symbol; and

a second circuit configured to sample the received first symbol of the second signal using a second timing signal having a second timing offset relative to the reference clock signal;

wherein the first circuit and second circuit are configured to accommodate all possible differences between the first timing offset and the second timing offset that falls within a range extending between a first value through a second value, wherein the second value equals the first value plus one clock cycle of the reference clock signal.

96. The device of claim 95, the first module including calibration apparatus configured to determine suitability of the first timing offset and adjust the first timing offset to make it more suitable for sampling the first signal.

97. A memory controller comprising:

a first circuit, in a first clock domain associated with a first timing offset relative to a reference clock signal, the first circuit configured to transmit a first symbol using a first timing signal having the first timing offset relative to the reference clock signal to drive the first symbol onto a first signal; and

a second circuit, coupled to the first circuit by the first signal, the second circuit in both the first time domain and in a second time domain associated with a second timing offset relative to the reference clock signal, the second circuit configured to receive the first symbol from the first signal and to transmit the first symbol to the memory component by driving the first symbol onto a second signal using a second timing signal having the second timing offset relative to the reference clock signal;

wherein the first circuit and second circuit are configured to accommodate all possible differences between the first timing offset and the second timing offset that falls within a range extending between a first value through a second value, wherein the second value equals the first value plus one clock cycle of the reference clock signal.

98. The memory controller of claim 97, including a first register configured to store the first timing offset.

99. The memory controller of claim 97, including calibration apparatus configured to determine suitability of the second timing offset and adjust the second timing offset to make it more suitable for driving the second signal.

100. The memory controller of claim 99, wherein the calibration apparatus is configured to periodically perform the suitability determination and adjusting the second timing offset between intervals in which normal memory read operations and memory write operations are performed.

101. The memory controller of claim 99, wherein the calibration apparatus is configured to send calibration information to the memory component and to then receive it back from the memory component in order to measure the suitability of the second timing offset.

102. The memory controller of claim 99, wherein the calibration apparatus is configured to determine suitability of the second timing offset by measuring the suitability of a first margin timing offset and by measuring the suitability of a second margin timing offset.

103. The memory controller of claim 102, wherein the first margin timing offset is stored in a first margin register and the second margin timing offset is stored in a second margin register and the calibration apparatus is configured to adjust the first margin timing offset to make it more suitable for driving the second signal.

104. The memory controller of claim 102, wherein the calibration apparatus is configured to combine the first margin timing offset and the second margin timing offset to generate the second timing offset.

105. A memory controller comprising:

a first circuit, in a first clock domain associated with a first timing offset relative to a reference clock signal, the first circuit configured to transmit a first symbol using a first timing signal having the first timing offset relative to the reference clock signal to drive the first symbol onto a first signal; and

a second circuit, coupled to the first circuit by the first signal, the second circuit in both the first time domain and in a second time domain associated with a second timing offset relative to the reference clock signal, the second circuit configured to receive the first symbol from the first signal and to transmit the first symbol to the memory component by driving the first symbol onto a second signal using a second timing signal having the second timing offset relative to the reference clock signal;

wherein the first circuit and second circuit are configured to accommodate all possible differences between the first timing offset and the second timing offset that falls within a range extending between a first value through a second value, wherein the second value equals the first value plus two clock cycles of the reference clock signal.

106. A controller comprising:

a first circuit, in a first clock domain associated with a first timing offset relative to a reference clock signal, the first circuit configured to transmit a first symbol using a first timing signal having the first timing offset relative to the reference clock signal to drive the first symbol onto a first signal; and

a second circuit, coupled to the first circuit by the first signal, the second circuit in both the first time domain and in a second time domain associated with a second timing offset relative to the reference clock signal, the second circuit configured to receive the first symbol from the first signal and to transmit the first symbol to the memory component by driving the first symbol onto a second signal using a second timing signal having the second timing offset relative to the reference clock signal;

wherein the first circuit and second circuit are configured to accommodate all possible differences between the first timing offset and the second timing offset that falls within a range extending between a first value through a second value, wherein the second value equals the first value plus one clock cycle of the reference clock signal.

107. The controller of claim 106, including calibration apparatus configured to determine suitability of the second timing offset and adjust the second timing offset to make it more suitable for driving the second signal.

108. A memory system comprising:

a memory controller;

a memory component having a memory core for holding read data information and an interface that is coupled to at least one bus that is also coupled to the memory controller for conveying signals between the memory controller and the memory component;

the memory controller comprising;

a first circuit, in a first clock domain associated with a first timing offset relative to a reference clock signal, the first circuit configured to transmit a first symbol using a first timing signal having the first timing offset relative to the reference clock signal to drive the first symbol onto a first signal; and

a second circuit, coupled to the first circuit by the first signal, the second circuit in both the first time domain and in a second time domain associated with a second timing offset relative to the reference clock signal, the second circuit configured to receive the first symbol from the first signal and to transmit the first symbol to the memory component by driving the first symbol onto a second signal using a second timing signal having the second timing offset relative to the reference clock signal;

wherein the first circuit and second circuit are configured to accommodate all possible differences between the first timing offset and the second timing offset that falls within a range extending between a first value through a second value, wherein the second value equals the first value plus one clock cycle of the reference clock signal.

109. The memory system of claim 108, wherein the memory controller includes calibration apparatus configured to determine suitability of the second timing offset and adjust the second timing offset to make it more suitable for driving the second signal.

110. The memory system of claim 109, wherein the calibration apparatus is configured to periodically perform the suitability determination and adjusting the second timing offset between intervals in which normal memory read operations and memory write operations are performed.

111. A system, comprising:

a first component;

a second component, the second component including storage for holding data information and an interface that is coupled to at least one bus that is also coupled to the first component;

the first component including;

a first circuit, in a first clock domain associated with a first timing offset relative to a reference clock signal, the first circuit configured to transmit a first symbol using a first timing signal having the first timing offset relative to the reference clock signal to drive the first symbol onto a first signal; and

a second circuit, coupled to the first circuit by the first signal, the second circuit in both the first time domain and in a second time domain associated with a second timing offset relative to the reference clock signal, the second circuit configured to receive the first symbol from the first signal and to transmit the first symbol to the memory component by driving the first symbol onto a second signal using a second timing signal having the second timing offset relative to the reference clock signal;

wherein the first circuit and second circuit are configured to accommodate all possible differences between the first timing offset and the second timing offset that falls within a range extending between a first value through a second value, wherein the second value equals the first value plus one clock cycle of the reference clock signal.

112. The system of claim 111, the first component includes calibration apparatus configured to determine suitability of the second timing offset and adjust the second timing offset to make it more suitable for driving the second signal.

113. A device comprising a single integrated circuit having a plurality of internal modules, the device comprising:

a first module; and

a second module having storage for holding data information and an interface that is coupled to at least one bus that is also coupled to the first module for conveying signals between the first module and the second module;

the first module comprising;

a first circuit, in a first clock domain associated with a first timing offset relative to a reference clock signal, the first circuit configured to transmit a first symbol using a first timing signal having the first timing offset relative to the reference clock signal to drive the first symbol onto a first signal; and

a second circuit, coupled to the first circuit by the first signal, the second circuit in both the first time domain and in a second time domain associated with a second timing offset relative to the reference clock signal, the second circuit configured to receive the first symbol from the first signal and to transmit the first symbol to the memory component by driving the first symbol onto a second signal using a second timing signal having the second timing offset relative to the reference clock signal;

wherein the first circuit and second circuit are configured to accommodate all possible differences between the first timing offset and the second timing offset that falls within a range extending between a first value through a second value, wherein the second value equals the first value plus one clock cycle of the reference clock signal.

114. The device of claim 113, wherein the first module includes calibration apparatus configured to determine suitability of the second timing offset and adjust the second timing offset to make it more suitable for driving the second signal.

115. A memory controller for use in conjunction with a memory component, comprising:

an interface configured to receive a first signal and a second signal from the memory component, wherein the first signal comprises a first symbol and the second signal comprises a second symbol;

a first circuit configured to receive the first signal by sampling the first symbol using a first timing offset relative to a reference clock signal;

a second circuit configured to receive the second signal by sampling the second symbol using a second timing offset relative to the reference clock signal;

wherein the first timing offset is different from the second timing offset.

116. The memory controller of claim 115, including a first register configured to store the first timing offset.

117. The memory controller of claim 115, including calibration apparatus configured to determine suitability of the first timing offset and adjust the first timing offset to make it more suitable for sampling the first signal.

118. The memory controller of claim 117, wherein the calibration apparatus is configured to periodically perform the suitability determination and adjusting the first timing offset between intervals in which normal memory read operations and memory write operations are performed.

119. The memory controller of claim 117, wherein the calibration apparatus is configured to send calibration information to the memory component and to then receive it back from the memory component in order to measure the suitability of the first timing offset.

120. The memory controller of claim 117, wherein the calibration apparatus is configured to determine suitability of the first timing offset by measuring the suitability of a first margin timing offset and by measuring the suitability of a second margin timing offset.

121. The memory controller of claim 120, wherein the first margin timing offset is stored in a first margin register and the second margin timing offset is stored in a second margin register and the calibration apparatus is configured to adjust the first margin timing offset to make it more suitable for sampling the first signal.

122. The memory controller of claim 120, wherein the calibration apparatus is configured to combine the first margin timing offset and the second margin timing offset to generate the first timing offset.

123. A memory system, comprising:

a memory component;

a memory controller coupled to the first memory component by a first signal and by a second signal;

the memory controller including;

a first circuit configured to receive a first symbol on the first signal by sampling the first signal using a first timing offset relative to a reference clock signal;

a second circuit configured to receive a second symbol on the second signal by sampling the second signal using a second timing offset relative to the reference clock signal;

wherein the first timing offset is different from the second timing offset.

124. The memory system of claim 123, including a first register configured to store the first timing offset.

125. The memory system of claim 123, including calibration apparatus configured to determine suitability of the first timing offset and adjust the first timing offset to make it more suitable for sampling the first signal.

126. The memory system of claim 125, wherein the calibration apparatus is configured to periodically perform the suitability determination and adjusting the first timing offset between intervals in which normal memory read operations and memory write operations are performed.

127. The memory system of claim 125, wherein the calibration apparatus is configured to send calibration information to the memory component and to then receive it back from the memory component in order to measure the suitability of the first timing offset.

128. The memory system of claim 125, wherein the calibration apparatus is configured to determine suitability of the first timing offset by measuring the suitability of a first margin timing offset and by measuring the suitability of a second margin timing offset.

129. The memory system of claim 128, wherein the first margin timing offset is stored in a first margin register and the second margin timing offset is stored in a second margin register and the calibration apparatus is configured to adjust the first margin timing offset to make it more suitable for sampling the first signal.

130. The memory system of claim 128, wherein the calibration apparatus is configured to combine the first margin timing offset and the second margin timing offset to generate the first timing offset.

131. A memory controller for use in conjunction with a memory component, comprising:

an interface configured to transmit a first signal and a second signal to the memory component, wherein the first signal comprises a first symbol and the second signal comprises a second symbol;

a first circuit configured to transmit the first signal by driving the first symbol using a first timing offset relative to a reference clock signal;

a second circuit configured to transmit the second signal by driving the second symbol using a second timing offset relative to the reference clock signal;

wherein the first timing offset is different from the second timing offset.

132. The memory controller of claim 131, including a first register configured to store the first timing offset.

133. The memory controller of claim 131, including calibration apparatus configured to determine suitability of the second timing offset and adjust the second timing offset to make it more suitable for driving the second signal.

134. The memory controller of claim 133, wherein the calibration apparatus is configured to periodically perform the suitability determination and adjusting the second timing offset between intervals in which normal memory read operations and memory write operations are performed.

135. The memory controller of claim 133, wherein the calibration apparatus is configured to send calibration information to the memory component and to then receive it back from the memory component in order to measure the suitability of the second timing offset.

136. The memory controller of claim 133, wherein the calibration apparatus is configured to determine suitability of the second timing offset by measuring the suitability of a first margin timing offset and by measuring the suitability of a second margin timing offset.

137. The memory controller of claim 136, wherein the first margin timing offset is stored in a first margin register and the second margin timing offset is stored in a second margin register and the calibration apparatus is configured to adjust the first margin timing offset to make it more suitable for driving the second signal.

138. The memory controller of claim 136, wherein the calibration-apparatus configured to combine the first margin timing offset and the second margin timing offset to generate the second timing offset.

139. A memory system, comprising:

a memory component;

a memory controller coupled to the first memory component by a first signal and by a second signal;

the memory controller including;

a first circuit configured to transmit the first signal by driving the first symbol using a first timing offset relative to a reference clock signal;

a second circuit configured to transmit the second signal by driving the second symbol using a second timing offset relative to the reference clock signal;

wherein the first timing offset is different from the second timing offset.

140. The memory system of claim 139, the memory controller including a first register configured to store the first timing offset.

141. The memory system of claim 139, the memory controller including calibration apparatus configured to determine suitability of the second timing offset and adjust the second timing offset to make it more suitable for driving the second signal.

142. The memory system of claim 141, wherein the calibration apparatus is configured to periodically perform the suitability determination and adjusting the second timing offset between intervals in which normal memory read operations and memory write operations are performed.

143. The memory system of claim 141, wherein the calibration apparatus is configured to send calibration information to the memory component and to then receive it back from the memory component in order to measure the suitability of the second timing offset.

144. The memory system of claim 141, wherein the calibration apparatus is configured to determine suitability of the second timing offset by measuring the suitability of a first margin timing offset and by measuring the suitability of a second margin timing offset.

145. The memory system of claim 144, wherein the first margin timing offset is stored in a first margin register and the second margin timing offset is stored in a second margin register and the calibration apparatus is configured to adjust the first margin timing offset to make it more suitable for driving the second signal.

146. The memory controller of claim 144, wherein the calibration apparatus configured to combine the first margin timing offset and the second margin timing offset to generate the second timing offset.

147. A memory system, comprising:

a memory controller having an interface that is coupled to a first data bus and a second data bus; and

a memory component having an interface that is coupled to the first data bus and the second data bus;

the system having a first mode of operation in which a first memory access causes a first data symbol associated with a first memory location to be transferred on the first data bus and causes a second data symbol associated with a second memory location to be transferred on the second data bus; and

the system having a second mode of operation in which a second memory access causes the first data symbol associated with the first memory location to be transferred on the first data bus and at a later time a third memory access causes the second data symbol associated with the second memory location to be transferred on the first data bus.

148. The memory system of claim 147, wherein the system is configured to change between the first mode of operation and the second mode of operation between memory accesses.

149. A memory controller comprising:

an interface that is coupled to a first data bus and a second data bus; and

logic having a first mode of operation and a second mode of operation, the first mode of operation comprising a mode of operation in which a first memory access causes a first data symbol associated with a first memory location to be transferred on the first data bus and causes a second data symbol associated with a second memory location to be transferred on the second data bus; and

the second mode of operation comprising a mode of operation in which a second memory access causes the first data symbol associated with the first memory location to be transferred on the first data bus and at a later time a third memory access causes the second data symbol associated with the second memory location to be transferred on the first data bus.

150. The memory controller of claim 149, wherein the logic is configured to change between the first mode of operation and the second mode of operation between memory accesses.

151. A memory component comprising,

a memory core for holding read data information;

an interface that is coupled to a first data bus and a second data bus; and

logic having a first mode of operation and a second mode of operation, the first mode of operation comprising a mode of operation in which a first memory access causes a first data symbol associated with a first memory location in the memory core to be transferred on the first data bus and causes a second data symbol associated with a second memory location in the memory core to be transferred on the second data bus; and

the second mode of operation comprising a mode of operation in which a second memory access causes the first data symbol associated with the first memory location to be transferred on the first data bus and at a later time a third memory access causes the second data symbol associated with the second memory location to be transferred on the first data bus.

152. The memory component of claim 151, wherein the logic is configured to change between the first mode of operation and the second mode of operation between memory accesses.

153. A memory system, comprising:

a memory controller having an interface that is coupled to a first data bus and a second data bus; and

a memory component having an interface that is coupled to the first data bus and the second data bus;

the system having a first mode of operation in which a first memory access causes a first data symbol associated with a first memory location to be transferred on the first data bus and causes a second data symbol associated with a second memory location to be transferred on the second data bus; and

the system having a second mode of operation in which a second memory access causes the first data symbol associated with the first memory location to be transferred on the first data bus and causes the second data symbol associated with the second memory location to be transferred on the first data bus after the first data symbol has been transferred on the first data bus.

154. The memory system of claim 153, wherein the system is configured to change between the first mode of operation and the second mode of operation between memory accesses.

155. A memory controller comprising:

an interface that is coupled to a first data bus and a second data bus; and

logic having a first mode of operation and a second mode of operation, the first mode of operation comprising a mode of operation in which a first memory access causes a first data symbol associated with a first memory location to be transferred on the first data bus and causes a second data symbol associated with a second memory location to be transferred on the second data bus; and

the second mode of operation comprising a mode of operation in which a second memory access causes the first data symbol associated with the first memory location to be transferred on the first data bus and causes the second data symbol associated with the second memory location to be transferred on the first data bus after the first data symbol has been transferred on the first data bus.

156. The memory controller of claim 155, wherein the logic is configured to change between the first mode of operation and the second mode of operation between memory accesses.

157. A memory component comprising,

a memory core for holding read data information;

an interface that is coupled to a first data bus and a second data bus; and

logic having a first mode of operation and a second mode of operation, the first mode of operation comprising a mode of operation in which a first memory access causes a first data symbol associated with a first memory location in the memory core to be transferred on the first data bus and causes a second data symbol associated with a second memory location in the memory core to be transferred on the second data bus; and

the second mode of operation comprising a mode of operation in which a second memory access causes the first data symbol associated with the first memory location to be transferred on the first data bus and causes the second data symbol associated with the second memory location to be transferred on the first data bus after the first data symbol has been transferred on the first data bus.

158. The memory component of claim 157, wherein the logic is configured to change between the first mode of operation and the second mode of operation between memory accesses.

159. A memory system, comprising:

a memory controller having an interface that is coupled to a first data bus; and

a memory component having an interface that is coupled to the first data bus;

the system having a first mode of operation in which a first memory access causes a first data symbol associated with a first memory location to be transferred on the first data bus and causes a second data symbol associated with a second memory location to be transferred on the first data bus after the first data symbol has been transferred; and

the system having a second mode of operation in which a second memory access causes the first data symbol associated with the first memory location to be transferred on the first data bus and at a later time a third memory access causes the second data symbol associated with the second memory location to be transferred on the first data bus.

160. The memory system of claim 159, wherein the system is configured to change between the first mode of operation and the second mode of operation between memory accesses.

161. A memory controller comprising:

an interface that is coupled to a first data bus; and

logic having a first mode of operation and a second mode of operation, the first mode of operation comprising a mode of operation in which a first memory access causes a first data symbol associated with a first memory location to be transferred on the first data bus and causes a second data symbol associated with a second memory location to be transferred on the first data bus after the first data symbol has been transferred; and

the second mode of operation comprising a mode of operation in which a second memory access causes the first data symbol associated with the first memory location to be transferred on the first data bus and at a later time a third memory access causes the second data symbol associated with the second memory location to be transferred on the first data bus.

162. The memory controller of claim 161, wherein the logic is configured to change between the first mode of operation and the second mode of operation between memory accesses.

163. A memory component comprising,

a memory core for holding read data information;

an interface that is coupled to a first data bus; and

logic having a first mode of operation and a second mode of operation, the first mode of operation comprising a mode of operation in which a first memory access causes a first data symbol associated with a first memory location to be transferred on the first data bus and causes a second data symbol associated with a second memory location to be transferred on the first data bus after the first data symbol has been transferred; and

the second mode of operation comprising a mode of operation in which a second memory access causes the first data symbol associated with the first memory location to be transferred on the first data bus and at a later time a third memory access causes the second data symbol associated with the second memory location to be transferred on the first data bus.

164. The memory component of claim 163, wherein the logic is configured to change between the first mode of operation and the second mode of operation between memory accesses.

165. A memory system, comprising:

a memory controller having an interface that is coupled to a first data bus and a second data bus; and

a memory module having an interface that is coupled to the first data bus and the second data bus;

the system having a first mode of operation in which a first memory access causes a first data symbol associated with a first memory location to be transferred on the first data bus and causes a second data symbol associated with a second memory location to be transferred on the second data bus; and

the system having a second mode of operation in which a second memory access causes the first data symbol associated with the first memory location to be transferred on the first data bus and at a later time a third memory access causes the second data symbol associated with the second memory location to be transferred on the second data bus.

166. The memory system of claim 165, wherein the system is configured to change between the first mode of operation and the second mode of operation between memory accesses.

167. A memory controller comprising:

an interface that is coupled to a first data bus and a second data bus; and

logic having a first mode of operation and a second mode of operation, the first mode of operation comprising a mode of operation in which a first memory access causes a first data symbol associated with a first memory location to be transferred on the first data bus and causes a second data symbol associated with a second memory location to be transferred on the second data bus; and

the second mode of operation comprising a mode of operation in which a second memory access causes the first data symbol associated with the first memory location to be transferred on the first data bus and at a later time a third memory access causes the second data symbol associated with the second memory location to be transferred on the second data bus.

168. The memory controller of claim 167, wherein the logic is configured to change between the first mode of operation and the second mode of operation between memory accesses.

169. A memory component comprising,

a memory core for holding read data information;

an interface that is coupled to a first data bus and a second data bus; and

logic having a first mode of operation and a second mode of operation, the first mode of operation comprising a mode of operation in which a first memory access causes a first data symbol associated with a first memory location to be transferred on the first data bus and causes a second data symbol associated with a second memory location to be transferred on the second data bus; and

the second mode of operation comprising a mode of operation in which a second memory access causes the first data symbol associated with the first memory location to be transferred on the first data bus and at a later time a third memory access causes the second data symbol associated with the second memory location to be transferred on the second data bus.

170. The memory component of claim 169, wherein the logic is configured to change between the first mode of operation and the second mode of operation between memory accesses.