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Test pattern compression for an integrated circuit test environment

  • US 20030131298A1
  • Filed: 01/31/2003
  • Published: 07/10/2003
  • Est. Priority Date: 11/23/1999
  • Status: Active Grant
First Claim
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1. A method that computes a compressed test pattern to test an integrated circuit, comprising:

  • (a) generating a preliminary set of equations associated with the compressed test pattern;

    (b) attempting to solve the set of equations;

    (c) if the attempt to solve the equations fails, deleting a most recently appended equation; and

    (d) if the attempt to solve the equations is successful, incrementally appending additional equations onto the set of equations;

    (e) repeating (b), (c) and (d) to generate a final set of equations;

    (f) solving the final set of equations to obtain the compressed test pattern.

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