Test pattern compression for an integrated circuit test environment
First Claim
1. A method that computes a compressed test pattern to test an integrated circuit, comprising:
- (a) generating a preliminary set of equations associated with the compressed test pattern;
(b) attempting to solve the set of equations;
(c) if the attempt to solve the equations fails, deleting a most recently appended equation; and
(d) if the attempt to solve the equations is successful, incrementally appending additional equations onto the set of equations;
(e) repeating (b), (c) and (d) to generate a final set of equations;
(f) solving the final set of equations to obtain the compressed test pattern.
2 Assignments
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Accused Products
Abstract
A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.
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Citations
19 Claims
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1. A method that computes a compressed test pattern to test an integrated circuit, comprising:
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(a) generating a preliminary set of equations associated with the compressed test pattern;
(b) attempting to solve the set of equations;
(c) if the attempt to solve the equations fails, deleting a most recently appended equation; and
(d) if the attempt to solve the equations is successful, incrementally appending additional equations onto the set of equations;
(e) repeating (b), (c) and (d) to generate a final set of equations;
(f) solving the final set of equations to obtain the compressed test pattern. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method that computes a compressed test pattern to test an integrated circuit, comprising:
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using simulation, generating symbolic expressions that are associated with simulated scan cells of an integrated circuit;
generating a test cube having the scan cells assigned predetermined values; and
formulating a set of equations by equating the assigned values in the scan cells to the symbolic expressions; and
determine if the equations are solvable, and if not, remove the last equation. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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Specification