Semiconductor device and method of manufacturing the same

• US 20030132450A1
• Filed: 10/17/2002
• Published: 07/17/2003
• Est. Priority Date: 02/21/2001
• Status: Active Grant

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Nitta, Tetsuya, Minato, Tadaharu
• Granted Patent: US 6,821,824 B2
• Time in Patent Office: Days
• US Class Current: 257/110
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7823 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors

Abstract

A semiconductor device of the present invention has a pn-repeating structure that a structure in which a p-type impurity region (4) and an n-type drift region (3) are aligned side by side is repeated twice or more, and a low concentration region which is either p-type impurity region (4) or n-type drift region (3) located at the outermost portion of this pn-repeating structure has the lowest impurity concentration or has the least generally effective charge amount among all the p-type impurity regions (4) and n-type drift regions (3) forming the pn-repeating structure.

Thereby, the main withstand voltage of a power semiconductor device to which a three dimensional multi-RESURF principle is applied, wherein the element withstand voltage is specifically in the broad range of 20 to 6000 V, can be improved and the trade-off relationship between the main withstand voltage and the ON resistance can also be improved, so that an inexpensive semiconductor device of which the power loss is small and of which the size of the chip is small can be obtained.

In addition, a trench of a dotted line trench (DLT) structure and a manufacturing method corresponding to this can be used, so that a semiconductor device with a good yield can be obtained at low cost.

Claims

1. A semiconductor device having a repeating structure wherein a structure where a first impurity region (3) of a first conductive type and a second impurity region (4) of a second conductive type are aligned side by side is repeated twice, or more, in a semiconductor substrate of the first conductive type, wherein

the semiconductor device is characterized in that a low concentration region (3, 4) that is either said first or second impurity region (3, 4) located at the outermost portion of said repeating structure has the lowest impurity concentration or has the least generally effective charge amount from among all of said first and second impurity regions (3, 4) forming said repeating structure.

2. The semiconductor device according to claim 1, characterized in that the impurity concentration of said low concentration region (3, 4) is no lower than 30% and no higher than 70% of the impurity concentration of a high concentration region (3, 4) that is either said first or second impurity region (3, 4) located closer to the center portion of said repeating structure than is said lower concentration region (3, 4).

3. The semiconductor device according to claim 2, characterized in that the impurity concentration of a middle concentration region (3, 4) that is either said first or second impurity regions (3, 4) located between said low concentration region (3, 4) and said high concentration region (3, 4) is higher than the impurity concentration of said low concentration region (3, 4) and is lower than the impurity concentration of said high concentration region (3, 4).

4. The semiconductor device according to claim 1, characterized in that

said semiconductor substrate has a first main surface and a second main surface facing each other,

a third impurity region (5) of the second conductive type is formed at least at a portion on said first main surface side in at least one of said plurality of first impurity regions (3) forming said repeating structure so as to form a main pn junction with said first impurity regions (3), and

a fourth impurity region (1) of the first conductive type is formed on said second main surface side of said repeating structure.

5. The semiconductor device according to claim 1, characterized in that said third impurity region (5) forming a main pn junction with said first impurity region (3) is a body region of an insulating gate type field effect transistor portion.

6. The semiconductor device according to claim 1, characterized in that said low concentration region (3, 4) located at the outermost portion of the repeating structure does not form an active element.

7. The semiconductor device according to claim 1, further comprising:

a third impurity region (5) of the second conductive type that is formed at least in a portion of an upper portion in the vicinity of an edge of said first impurity region (3) extending in one specific direction;

a fourth impurity region (54) of the first conductive type that is formed in at least a portion of an upper portion in the vicinity of an edge of said first impurity region (3) in the direction opposite to said one specific direction;

a first electrode electrically connected to said third impurity region (5); and

a second electrode electrically connected to said fourth impurity region (54), wherein

the semiconductor device is characterized in that said first and second electrodes are both formed on said first main surface.

8. The semiconductor device according to claim 1, characterized in that

said semiconductor substrate has a first main surface and a second main surface facing each other and has a plurality of trenches (23) in said first main surface, and

said repeating structure has a structure wherein a structure where said first and second impurity regions (3, 4) is aligned with said trench (23) located in between is repeated twice or more.

9. The semiconductor device according to claim 8, characterized in that the impurity concentration of said low concentration region (3, 4) is no lower than 30% and no higher than 70% of the impurity concentration of a high concentration region (3, 4) that is either said first or second impurity region (3, 4) located closer to the center portion in said repeating structure than said low concentration region (3, 4).

10. The semiconductor device according to claim 9, characterized in that the impurity concentration of a middle concentration region (3, 4) that is either said first or second impurity region (3, 4) located between said low concentration region (3, 4) and said high concentration region (3, 4) is higher than the impurity concentration of said low concentration region (3, 4) and is lower than the impurity concentration of said high concentration region (3, 4).

11. The semiconductor device according to claim 8, characterized in that said first impurity region (3) is formed on one side of a mesa portion of said semiconductor substrate surrounded by said plurality of trenches (23), said second impurity region (4) is formed on the opposite side of the mesa portion and a third impurity region (5) of the second conductive type is formed in at least a portion on said first main surface side of said first impurity region (3) so as to form a main pn junction with said first impurity region (3).

12. The semiconductor device according to claim 11, characterized in that said third impurity region (5) forming the main pn junction with said first impurity region (3) is a body region of an insulating gate-type field effect transistor portion.

13. The semiconductor device according to claim 8, characterized in that said low concentration region (3, 4) located at the outermost portion of the repeating structure does not form an active element.

14. The semiconductor device according to claim 8, characterized in that a trench (23) located at the outermost portion of said plurality of trenches (23) is a first trench of a dotted line form having a surface pattern of a dotted line form wherein a plurality of first holes (23a) is arranged at intervals in a predetermined direction in said first main surface and said low concentration region (3, 4) is formed so as to be located on one of the sidewalls of said first trench (23) of a dotted line form.

15. The semiconductor device according to claim 14, characterized in that the sum of the lengths of the sidewalls on one side of said plurality of first holes (23a) that form said first trench (23) of a dotted line form in said first main surface is no less than 30% and no greater than 70% of the length of the sidewall on one side of a continuously extending trench (23) located closer to the center portion than is said first trench (23) of a dotted line form in said first main surface.

16. The semiconductor device according to claim 14, characterized in that

a trench located between said first trench (23) of the doted line form and said continuously extending trench (23) is a second trench (23) of a dotted line form having a surface pattern of a dotted line form wherein a plurality of second holes (23a₁, 23a₂) is arranged at intervals in a predetermined direction in said first main surface, and

the sum of the lengths of the sidewalls on one side of said plurality of second holes (23a₁, 23a₂) forming said second trench (23) of a dotted line form in said first main surface is greater than the sum of the lengths of the sidewalls on one side of said plurality of first holes (23a₃) forming said first trench (23) of a dotted line form in said first main surface and is smaller than the length of the sidewall on one side of a continuously extending trench (23) located closer to the center portion than is said second trench (23) of a dotted line form in said first main surface.

17. The semiconductor device according to claim 14, characterized in that said first impurity region (3) is formed on one side of the mesa portion of said semiconductor substrate surrounded by said plurality of trenches (23), said second impurity region is formed on the opposite side of the mesa portion and a third impurity region (5) of the second conductive type is formed in at least a portion on said first main surface side of said first impurity region (3) so as to form a main pn junction with said first impurity region (3).

18. The semiconductor device according to claim 17, characterized in that said third impurity region (5) forming the main pn junction with said first impurity region (3) is a body region of an insulating gate-type field effect transistor portion.

19. The semiconductor device according to claim 14, characterized in that said low concentration region (3, 4) located at the outermost portion of the repeating structure does not form an active element.

20. The semiconductor device according to claim 1, characterized in that

said semiconductor substrate has a first main surface and a second main surface facing each other and has a plurality of trenches including first and second trenches (23) adjoining each other in said first main surface, and

a structure where said first impurity region (3) is formed on each of the two sidewalls of said first trench (23) and said second impurity region (4) is formed on each of the two sidewalls of said second trench (23) is repeated twice or more.

21. The semiconductor device according to claim 20, characterized in that the impurity concentration of said low concentration region (3, 4) is no lower than 30% and no higher than 70% of the impurity concentration of a high concentration region (3, 4) that is either said first or second impurity region (3, 4) located closer to the center portion of said repeating structure than is said lower concentration region (3, 4).

22. The semiconductor device according to claim 21, characterized in that the impurity concentration of a middle concentration region (3, 4) that is either said first or second impurity region (3, 4) located between said low concentration region (3, 4) and said high concentration region (3, 4) is higher than the impurity concentration of said low concentration region (3, 4) and is lower than the impurity concentration of said high concentration region (3, 4).

23. The semiconductor device according to claim 20, characterized in that said first impurity region (3) is formed on one side of the mesa portion of said semiconductor substrate surrounded by said plurality of trenches (23), said second impurity region (4) is formed on the opposite side of the mesa portion and a third impurity region (5) of the second conductive type is formed in at least a portion on said first main surface side of said first impurity region (3) so as to form a main pn junction with said first impurity region (3).

24. The semiconductor device according to claim 23, characterized in that said third impurity region (5) forming a main pn junction with said first impurity region (3) is a body region of an insulating gate-type field effect transistor portion.

25. The semiconductor device according to claim 20, characterized in that said low concentration region (3, 4) located at the outermost portion of the repeating structure does not form an active element.

26. The semiconductor device according to claim 20, characterized in that the trench (23) located at the outermost portion of said plurality of trenches (23) is a first trench (23) of a dotted line form having a surface pattern of a dotted line form wherein said plurality of first holes (23a) is arranged at intervals in a predetermined direction in said first main surface and said low concentration region (3, 4) is formed so as to be located in a sidewall on⁻

one side of said first trench (23) of a dotted line form.

27. The semiconductor device according to claim 26, characterized in that the sum of the lengths of the sidewalls on one side of said plurality of first holes (23a) forming said first trench (23) of a dotted line form in said first main surface is no less than 30% and no greater than 70% of the length of a sidewall on one side of a trench (23) continuously extending located closer to the center portion than said first trench (23) of a dotted line form in said first main surface.

28. The semiconductor device according to claim 26, characterized in that

a trench (23) located between said first trench (23) of a dotted line form and said continuously extending trench (23) is a second trench (23) of a dotted line form having a surface pattern of a dotted line form wherein a plurality of second holes (23a₁, 23a₂) is arranged at intervals in a predetermined direction in said first main surface, and

the sum of the lengths of the sidewalls on one side of said plurality of second holes (23a₁, 23a₂) forming said second trench (23) of a dotted line form in said first main surface is greater than the sum of the lengths of the sidewalls on one side of said plurality of first holes (23a₃) forming said first trench (23) of a dotted line form in said first main surface and is smaller than the length of the sidewall on one side of the continuously extending trench (23) located closer to the center portion than said second trench (23) of a dotted line form in said first main surface.

29. The semiconductor device according to claim 26, characterized in that said first impurity region (3) is formed on one side of the mesa portion of said semiconductor substrate surrounded by said plurality of trenches (23), said second impurity region is formed on the opposite side of the mesa portion and a third impurity region (5) of the second conductive type is formed in at least a portion on said first main surface side of said first impurity region (3) so as to form a main pn junction with said first impurity region (3).

30. The semiconductor device according to claim 26, characterized in that said third impurity region (5) forming the main pn junction with said first impurity region (3) is a body region of an insulating gate-type field effect transistor portion.

31. The semiconductor device according to claim 26, characterized in that said low concentration region (3, 4) located at the outermost portion of the repeating structure does not form an active element.

32. A manufacturing method for a semiconductor device having a structure wherein a structure where a first impurity region (3) of a first conductive type and a second impurity region (4) of a second conductive type are aligned side by side is repeated twice or more in a semiconductor substrate of the first conductive type, characterized in that

a low concentration region (3, 4) that is either said first or second impurity region (3, 4) located at the outermost portion of said repeating structure and said first and second impurity regions (3, 4), other than the low concentration region, are formed so as to have independently changed concentrations so that said low concentration region (3, 4) has the lowest impurity concentration or has the least generally effective charge amount among all of said first and second impurity regions (3, 4) forming said repeating structure.

33. The manufacturing method for a semiconductor device according to claim 32, characterized in that said low concentration region (3, 4) and said other first and second impurity-regions (3, 4) are formed by means of ion implantation and heat treatment wherein the concentrations have been independently changed in order to form said low concentration region (3, 4) and said other first and second impurity regions (3, 4) of which the concentrations have been independently changed.

34. The manufacturing method for a semiconductor device according to claim 32, characterized in that said low concentration region (3, 4) and said other first and second impurity regions (3, 4) are formed by means of ion implantation and multi-stage epitaxial growth wherein the concentrations have been independently changed in order to form said low concentration region (3, 4) and said other first and second impurity regions (3, 4) of which the concentrations have been independently changed.

35. The manufacturing method for a semiconductor device according to claim 32, characterized in that said low concentration region (3, 4) and said other first and second impurity regions (3, 4) are formed by means of ion implantation wherein the concentrations have been independently changed and the implantation energies have been changed according to multiple levels in order to form said low concentration region (3, 4) and said other first and second impurity regions (3, 4) of which the concentrations have been independently changed.

36. The manufacturing method for a semiconductor device according to claim 32, characterized in that said other first and second impurity regions (3, 4) are formed of impurity ions implanted through first openings of a mask (31q) for ion implantation and said low concentration region (3, 4) is formed of impurity ions implanted through second openings of which the total opening area is smaller than that of said first openings in order to form said low concentration region (3, 4) and said other first and second impurity regions (3, 4) of which the concentrations have been independently changed.

37. The manufacturing method for a semiconductor device according to claim 36, characterized in that

said second openings have a configuration wherein a plurality of microscopic openings separated from each other are densely arranged, and

impurity ions implanted through all of said plurality of microscopic openings are integrated by carrying out a heat treatment so as to form said low concentration region (3, 4) of which the finished average impurity concentration is lower than that of said other first and second impurity regions (3, 4).

38. The manufacturing method for a semiconductor device according to claim 32, characterized by further comprising the steps of

simultaneously forming one, or more, trench(es) (23) and a trench (23) of a dotted line form that is located along the outside of said one, or more, trench(es) (23) wherein a plurality of first holes (23a) is arranged at intervals in a predetermined direction and that, thereby, has a surface pattern of a dotted line form in said first main surface;

and

simultaneously forming said low concentration region (3, 4) in the sidewall on one side of said trench (23) of a dotted line form and said other first and second impurity regions (3, 4) in the sidewalls on one side of said one, or more, trenches (23) by simultaneously carrying out an ion implantation in the sidewalls on one side of the respective trenches of said one, or more, trench (23) and said trench (23) of a dotted line form.

39. The manufacturing method for a semiconductor device according to claim 32, characterized by further comprising the steps of:

creating two, or more, trenches (23) in the first main surface of said semiconductor substrate;

ion implantation of impurities into the sidewalls on one side of said two, or more, trenches (23) in order to form said first or second impurity regions (3, 4); and

forming said low concentration region (3, 4) by carrying out an ion implantation of impurities of a conductive type opposite to that of the already implanted impurities in the sidewall on one side of said trench (23) located at the outermost portion under the condition wherein said two, or more, trenches (23) except the trench (23) located at the outermost portion are filled in with a filling layer so that the concentration of the already implanted impurities is substantially lowered.

40. The manufacturing method for a semiconductor device according to claim 32, characterized by further comprising the steps of:

creating one, or more, trench(es) (23) in a first main surface of said semiconductor substrate;

ion implantation of a first implantation amount for forming said first or second impurity region (3, 4) in the sidewalls on one side of said one, or more, trenches (23);

creating a new trench (23) at the outermost portion outside of said one, or more, trench(es) (23) under the condition wherein each of said one, or more, trench(es) (23) is filled in with a filling layer; and

ion implantation of a second implantation amount that is smaller than said first implantation amount for forming said low concentration region (3, 4) in the sidewall on one side of said trench (23) at the outermost portion.

41. The manufacturing method for a semiconductor device according to claim 32, characterized by further comprising the steps of:

simultaneously creating two, or more, trenches (23) including first and second trenches (23) adjoining each other in a first main surface of said semiconductor substrate and a trench (23) of a dotted line form having a surface pattern of a dotted line form in said first main surface by arranging a plurality of first holes (23a) at intervals in a predetermined direction so as to be located along the outside of said two, or more, trenches (23);

ion implantation of first impurities for forming said first impurity region (3) in each of the sidewalls on both sides of said first trench (23); and

ion implantation of second impurities for forming said second impurity region (4) in each of the sidewalls on both sides of said second trench (23), wherein

said low concentration regions (3, 4) are created in the sidewalls on both sides of said trench (23) of a dotted line through implantation at the same time of the ion implantation of said first or second impurities.

42. The manufacturing method for a semiconductor device according to claim 32, characterized by further comprising the steps of:

creating a first group of trenches made of a plurality of first trenches (23) in a first main surface of said semiconductor substrate;

ion implantation into each of the sidewalls on both sides of said first trenches (23) for forming said first impurity regions (3);

creating a second group of trenches made of a plurality of second trenches (23) in said first main surface so that said first trenches (23) and said second trenches (23) are positioned in an alternating manner;

ion implantation in each of the sidewalls on both sides of said second trenches (23) for forming said second impurity regions (4);

implanting ions of a conductive type opposite to that of the already implanted impurities in the sidewalls on both sides of said trench (23) located at the outermost portion under the condition wherein said first and second trenches (23) arranged in an alternating manner except the trench (23) located at the outermost portion are filled in with a filling layer so as to form said low concentration regions (3, 4) by substantially lowering the concentration of the already implanted impurities.

43. The manufacturing method for a semiconductor device according to claim 32, characterized by further comprising the steps of:

creating a first group of trenches made of a plurality of first trenches (23) in a first main surface of said semiconductor substrate;

ion implantation for forming said first impurity regions (3) in the sidewalls on both sides of each of said first trenches (23);

creating a second group of trenches made of a plurality of second trenches (23) in said first main surface in the condition that each of said first trenches (23) is filled in with a filling layer so that said first trenches (23) and said second trenches (23) are alternately located;

ion implantation for forming said second impurity regions (4) in the sidewalls on both sides of each of said second trenches (23);

creating a new trench (23) at the outermost portion outside of the trench (23) located at the outermost portion of said first and second trenches (23) that are arranged in an alternating manner under the condition wherein each of said first and second trenches (23) is filled in with a filling layer; and

forming said low concentration region (3, 4) of which the impurity concentration is lower than that of said first or second impurity regions (3, 4) by implanting impurity ions of said first or second conductive type into the sidewalls on both sides of said trench (23) at the outermost portion.

44. The manufacturing method for a semiconductor device according to claim 32, characterized by further comprising the steps of:

simultaneously creating a first group of trenches made of a plurality of first trenches (23) and a second group of trenches made of a plurality of second trenches (23) in a first main surface of said semiconductor substrate so that said first trenches (23) and said second trenches (23) are alternately located;

ion implantation for forming said first impurity regions (3) into the sidewalls on both sides of each of said plurality of first trenches (23) forming said first group of trenches under a condition wherein said second group of trenches is filled in with a first filling layer;

ion implantation for forming said second impurity regions (4) into the sidewalls on both sides of each of said plurality of second trenches (23) forming said second group of trenches under a condition wherein said first group of trenches is filled in with a second filling layer;

forming said low concentration regions (3, 4) by implanting impurity ions of a conductive type opposite to that of the already implanted impurities into the sidewalls on both sides of said trench (23) at the outermost portion so that the concentration of the already implanted impurities is lowered under the condition wherein all the trenches of said plurality of first trenches (23) forming said first group of trenches and of said plurality of second trenches (23) forming said second group of trenches except the trench (23) at the outermost portion located in the outermost portion.

45. The manufacturing method for a semiconductor device according to claim 32, characterized by further comprising the steps of:

simultaneously creating a first group of trenches made of a plurality of first trenches (23) and a second group of trenches made of a plurality of second trenches (23) in a first main surface of said semiconductor substrate so that said first trenches (23) and said second trenches (23) are alternately located;

ion implantation for forming said first impurity regions (3) into the sidewalls on both sides of each of said plurality of first trenches (23) forming said first group of trenches under a condition wherein said second group of trenches is filled in with a first filling layer; and

ion implantation for forming said second impurity regions (4) into the sidewalls on both sides of each of said plurality of second trenches (23) forming said second group of trenches under a condition wherein said first group of trenches is filled in with a second filling layer, wherein

the trench (23) at the outermost portion located at the outermost portion from among said plurality of first trenches (23) forming said first group of trenches and said plurality of second trenches (23) forming said second group of trenches is a trench (23) of a dotted line form having a surface pattern of a dotted line form wherein a plurality of holes (23a) is arranged at intervals in a predetermined direction in said first main surface.

46. The manufacturing method for a semiconductor device according to claim 32, characterized by further comprising the steps of:

creating two, or more, trenches (23) in a first main surface of said semiconductor substrate;

ion implantation of impurities into the sidewalls on one side of said two, or more, trenches (23) for forming said first or second impurity regions (3, 4); and

ion implantation of impurities of the same conductive type as that of the already implanted impurities into the sidewalls on one side of the trenches (23) other than said trench (23) located at the outermost portion under the condition wherein the trench (23) located at the outermost portion from among said two, or more, trenches (23) is filled in with a filling layer and, thereby, the concentration of the already implanted impurities is substantially increased so that said first or second impurity region (3, 4) in the sidewall of said trench (23) located at the outermost portion becomes a region of a comparatively low concentration.

47. The manufacturing method for a semiconductor device according to claim 32, characterized by further comprising the steps of:

creating a first group of trenches made of a plurality of first trenches (23) in a first main surface of said semiconductor substrate;

ion implantation for forming said first impurity regions (3) in the sidewalls on both sides of each of said first trenches;

creating a second group of trenches made of a plurality of second trenches (23) in said first main surface so that said first trenches (23) and said second trenches (23) are arranged in an alternating manner;

ion implantation for forming said second impurity regions (4) in the sidewalls on both sides of each of said second trenches (23);

ion implantation of impurities of the same conductive type as that of the already implanted impurities into the sidewalls on both sides of the trenches (23) other than said trench (23) located at the outermost portion under the condition wherein the trench (23) located at the outermost portion from among said first and second trenches (23) arranged in an alternating manner is filled in with a filling layer and, thereby, the concentration of the already implanted impurities is substantially increased so that said first or second impurity region (3, 4) in the sidewall of said trench (23) located at the outermost portion becomes a region of a comparatively low concentration.

48. The manufacturing method for a semiconductor device according to claim 32, characterized by further comprising the steps of:

simultaneously creating a first group of trenches made of a plurality of first trenches (23) and a second group of trenches made of a plurality of second trenches (23) in a first main surface of said semiconductor substrate so that said first trenches (23) and said second trenches (23) are alternately located;

ion implantation for forming said first impurity regions (3) into the sidewalls on both sides of each of said plurality of first trenches (23) forming said first group of trenches under a condition wherein said second group of trenches is filled in with a first filling layer;

ion implantation for forming said second impurity regions (4) into the sidewalls on both sides of each of said plurality of second trenches (23) forming said second group of trenches under a condition wherein said first group of trenches is filled in with a second filling layer;

implanting impurity ions of the same conductive type as that of the already implanted impurities into the sidewalls on both sides of the trenches (23) other than said trench (23) at the outermost portion under the condition wherein the trench (23) at the outermost portion, located at the outermost portion, from among said plurality of first trenches (23) forming said first group of trenches and said plurality of second trenches (23) forming said second group of trenches is filled in with a third filling layer so as to increase the concentration of the already implanted impurities so that said first or second impurity regions (3, 4) of the sidewalls of the trench (23) at the outermost portion become regions of a comparatively low concentration.