Field-effect transistor, circuit configuration and method of fabricating a field-effect transistor

• US 20030132461A1
• Filed: 01/28/2003
• Published: 07/17/2003
• Est. Priority Date: 07/28/2000
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Roesner, Wolfgang, Luyken, Richard Johannes, Kretz, Johannes
• Granted Patent: US 6,740,910 B2
• Time in Patent Office: Days
• US Class Current: 257/213
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H10K 10/462 Insulated gate field-effect transistors [IGFETs]
• CPC Class Codes: H10K 85/221 Carbon nanotubes
• CPC Class Codes: H10K 85/615 Polycyclic condensed aromatic hydrocarbons, e.g. anthracene
• CPC Class Codes: Y10S 977/938 Field effect transistors, FETS, with nanowire- or nanotube-channel region

Abstract

The gate region of a field effect transistor comprises at least one through hole wherein a nanoelement is provided which is electrically coupled to the source and the drain. The nanoelement may have the conductance thereof controlled by means of the gate, such that the nanoelement forms a channel region of the field effect transistor.

Claims

1. A field-effect transistor, comprising:

a source region;

a drain region;

a gate region between said source region and said drain region;

said gate region containing conductive material having at least one through hole formed therein;

at least one nanoelement disposed in said through hole and electrically coupled to said source region and said drain region is; and

said nanoelement being arranged and configured such that a conductivity thereof is controlled via said gate region, and said nanoelement forms a channel region.

2. The field-effect transistor according to claim 1, wherein said nanoelement comprises at least one of a nanotube and a nanowire.

3. The field-effect transistor according to claim 1, wherein said gate region is a conductive layer.

4. The field-effect transistor according to claim 1, wherein said nanoelement comprises a semiconducting nanowire.

5. The field-effect transistor according to claim 4, wherein said nanowire is a silicon nanowire.

6. The field-effect transistor according to claim 1, wherein said nanoelement comprises a semiconducting nanotube.

7. The field-effect transistor according to claim 6, wherein said nanotube is a carbon nanotube.

8. The field-effect transistor according to claim 1, wherein said nanoelement has a heterostructure, with:

a first metallically conductive region;

a second metallically conductive region; and

an electrically insulating region between said first metallically conductive region and said second metallically conductive region.

9. The field-effect transistor according to claim 8, wherein:

said first metallically conductive region of said nanotube is a metallically conductive carbon nanotube;

said second metallically conductive region of said nanotube is a metallically conductive carbon nanotube; and

said electrically insulating region of said nanotube is a boron nitride nanotube.

10. The field-effect transistor according to claim 1, wherein said source region contains a material acting catalytically for forming a nanotube.

11. The field-effect transistor according to claim 10, wherein said material contains at least one metal selected from the group consisting of nickel, cobalt, iron, and an alloy thereof.

12. The field-effect transistor according to claim 1, wherein said gate region contains at least one material selected from the group consisting of aluminum, titanium, tungsten, gold, silver, and an alloy thereof.

13. The field-effect transistor according to claim 1, wherein said drain region contains at least one material selected from the group consisting of nickel, cobalt, and an alloy thereof.

14. A circuit configuration comprising at least one field-effect transistor according to claim 1.

15. A method of fabricating a field-effect transistor, which comprises:

forming a source layer on a substrate;

forming an electrically conductive gate layer is on the source layer;

forming at least one through hole in the gate layer;

introducing at least one nanoelement into the through hole, the nanoelement being electrically coupled to the source layer and arranged and configured such that a conductivity thereof is controllable via the gate region, so that the nanoelement forms a channel region; and

applying a drain layer on the gate layer and electrically coupling the drain layer to the nanoelement.

16. The method according to claim 15, wherein the step of forming the through hole comprises dry etching.