High frequency tunable filter

• US 20030132797A1
• Filed: 12/18/2001
• Published: 07/17/2003
• Est. Priority Date: 12/18/2001
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Mohieldin, Ahmed N., Bellaouar, Abdellatif, Frechette, Michel, Embabi, Sherif
• Granted Patent: US 6,646,498 B2
• Time in Patent Office: Days
• US Class Current: 327/552
• CPC Class Codes: H03B 5/04 Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
• CPC Class Codes: H03B 5/24 active element in amplifier being semiconductor device H03B5/26 takes precedence
• CPC Class Codes: H03H 11/1213 using transistor amplifiers H03H11/1204 takes precedence; parallel-T filters H03H11/1295
• CPC Class Codes: H03H 11/1286 Sallen-Key biquad

Abstract

An integrated circuit (ICT) comprising a filter (50). The filter comprises an input (ν_in+) for receiving an input signal and an output (56) for producing an output signal having a frequency cutoff point. The filter further comprises at least one resistor network (RN₁) coupled between the input and the output. The resistor network comprises a first non-switched resistance (R_1.1) and a first resistance series connection connected in parallel with the first non-switched resistance. The first resistance series connection comprises a switched resistance (R_1.2) connected in series with a source/drain path of a switching transistor (TRR_1.2), the switching transistor having a gate for receiving a control signal. The frequency cutoff point is adjustable in response to the control signal. Additionally, the switched resistance has a first resistance and the switching transistor has an on-resistance. Further, the on-resistance is at least 20 percent of the total of the first resistance and the on-resistance.

Claims

1. An integrated circuit comprising a filter, the filter comprising:

an input for receiving an input signal;

an output for producing an output signal having a frequency cutoff point;

at least one resistor network coupled between the input and the output, the resistor network comprising;

a first non-switched resistance;

a first resistance series connection connected in parallel with the first non-switched resistance, the first resistance series connection comprising a switched resistance connected in series with a source/drain path of a switching transistor, the switching transistor having a gate for receiving a control signal;

wherein the frequency cutoff point is adjustable in response to the control signal;

wherein the switched resistance has a first resistance;

wherein the switching transistor has an on-resistance; and

wherein the on-resistance is at least 20 percent of the total of the first resistance and the on-resistance.

2. The filter of claim 1:

wherein the switched resistance has a first resistance;

wherein the switching transistor has an on-resistance; and

wherein the on-resistance is between 20 percent and 80 percent of the total of the first resistance and the on-resistance.

3. The filter of claim 1:

wherein the switched resistance has a first resistance;

wherein the switching transistor has an on-resistance; and

wherein the on-resistance is approximately 50 percent of the total of the first resistance and the on-resistance.

4. The filter of claim 1:

wherein the switched resistance has a first resistance;

wherein the non-switched resistance has a second resistance;

wherein the switching transistor has an on-resistance; and

wherein the total of the first resistance and the on-resistance is greater than the second resistance.

5. The filter of claim 1 and further comprising:

at least one capacitor network coupled between the input and the output, the capacitor network comprising;

a first non-switched capacitance;

a first capacitance series connection connected in parallel with the first non-switched capacitance, the first capacitance series connection comprising a switched capacitance connected in series with a source/drain path of a switching transistor, the switching transistor having a gate for receiving a control signal; and

wherein the frequency cutoff point is further adjustable in response to the control signal coupled to the gate of the switching transistor in the first capacitance series connection.

6. The filter of claim 5 wherein the control signal coupled to the gate of the switching transistor in the first capacitance series connection is a complement of the control signal coupled to the gate of the switching transistor in the first resistance series connection.

7. The filter of claim 6 wherein the switching transistor in the first resistance series connection and the switching transistor in the first capacitance series connection are like conductivity-type transistors.

8. The filter of claim 6 wherein the switching transistor in the first resistance series connection and the switching transistor in the first capacitance series connection are PMOS transistors.

9. The filter of claim 5:

wherein the at least one capacitance network further comprises a plurality of capacitance series connections, the plurality comprising the first capacitance series connection;

wherein each of the plurality of capacitance series connections is connected in parallel with the first non-switched capacitance;

wherein each of the plurality of capacitance series connections comprises a switched capacitance connected in series with a source/drain path of a corresponding switching transistor, the corresponding switching transistor having a gate for receiving a control signal; and

wherein the frequency cutoff point is adjustable in response to the control signals coupled to each switching transistor in the plurality of capacitance series connections.

10. The integrated circuit of claim 5 and further comprising an oscillator, wherein the oscillator comprises a resistor network, the resistor network comprising:

a second non-switched resistance;

a second resistance series connection connected in parallel with the second non-switched resistance, the second resistance series connection comprising a switched resistance connected in series with a source/drain path of a switching transistor, the switching transistor of the second resistance series connection having a gate for receiving a control signal; and

wherein the control signal connected to the gate of the switching transistor in the first resistance series connection is adjusted in response to the control signal connected to the gate of the switching transistor in the second resistance series connection.

11. The integrated circuit of claim 10, wherein the oscillator further comprises a capacitor network, the capacitor network comprising:

a second non-switched capacitance;

a second capacitance series connection connected in parallel with the second non-switched capacitance, the second capacitance series connection comprising a switched capacitance connected in series with a source/drain path of a switching transistor, the switching transistor of the second capacitance series connection having a gate for receiving a control signal; and

wherein the control signal coupled to the gate of the switching transistor in the second capacitance series connection is a complement of the control signal coupled to the gate of the switching transistor in the second resistance series connection.

12. The integrated circuit of claim 11 and further comprising circuitry for determining the control signal in response to an oscillation frequency output by the oscillator.

13. The integrated circuit of claim 11 wherein the switching transistor in the second resistance series connection and the switching transistor in the second capacitance series connection are like conductivity-type transistors.

14. The integrated circuit of claim 11 wherein the switching transistor in the second resistance series connection and the switching transistor in the second capacitance series connection are PMOS transistors.

15. The filter of claim 1:

wherein the at least one resistor network further comprises a plurality of resistance series connections, the plurality comprising the first resistance series connection;

wherein each of the plurality of resistance series connections is connected in parallel with the first non-switched resistance;

wherein each of the plurality of resistance series connections comprises a switched resistance connected in series with a source/drain path of a corresponding switching transistor, the corresponding switching transistor having a gate for receiving a control signal; and

wherein the frequency cutoff point is adjustable in response to the control signals coupled to each switching transistor in the plurality of resistance series connections.

16. The filter of claim 1:

wherein the at least one resistor network comprises a first resistor network coupled between the input node and a first node;

and further comprising;

a second resistor network coupled between the first node and a base of a bipolar junction transistor, the second resistor network comprising;

a second non-switched resistance; and

a second resistance series connection connected in parallel with the second non-switched resistance, the second resistance series connection comprising a switched resistance connected in series with a source/drain path of a switching transistor, the switching transistor having a gate for receiving the control signal.

17. The filter of claim 16 and further comprising at least one capacitor network coupled between the base of the bipolar junction transistor and a node for receiving a DC voltage, the capacitor network comprising:

a first non-switched capacitance; and

a first capacitance series connection connected in parallel with the first non-switched capacitance, the first capacitance series connection comprising a switched capacitance connected in series with a source/drain path of a switching transistor, the switching transistor having a gate for receiving a complement of the control signal.

18. The filter of claim 17 wherein the output comprises an emitter of the bipolar junction transistor.

19. The filter of claim 17 and further comprising a non-switched capacitor coupled between the first node and an emitter of the bipolar junction transistor.

20. The integrated circuit of claim 1 and further comprising an oscillator, wherein the oscillator comprises a resistor network, the resistor network comprising:

a second non-switched resistance;

a second resistance series connection connected in parallel with the second non-switched resistance, the second resistance series connection comprising a switched resistance connected in series with a source/drain path of a switching transistor, the switching transistor of the second resistance series connection having a gate for receiving a control signal; and

wherein the control signal connected to the gate of the switching transistor in the first resistance series connection is adjusted in response to the control signal connected to the gate of the switching transistor in the second resistance series connection.

21. The integrated circuit of claim 20 and further comprising circuitry for determining the control signal in response to an oscillation frequency output by the oscillator.

22. A integrated circuit comprising a filter, the filter comprising:

an input for receiving an input signal;

an output for producing an output signal having a frequency cutoff point;

at least one resistor network coupled between the input and the output, the resistor network comprising;

a first non-switched resistance;

a first resistance series connection connected in parallel with the first non-switched resistance, the first resistance series connection comprising a switched resistance connected in series with a source/drain path of a switching transistor, the switching transistor having a gate for receiving a control signal, wherein the frequency cutoff point is adjustable in response to the control signal;

at least one capacitor network coupled between the input and the output, the capacitor network comprising;

a first non-switched capacitance;

a first capacitance series connection connected in parallel with the first non-switched capacitance, the first capacitance series connection comprising a switched capacitance connected in series with a source/drain path of a switching transistor, the switching transistor having a gate for receiving a control signal; and

wherein the frequency cutoff point is further adjustable in response to the control signal coupled to the gate of the switching transistor in the first capacitance series connection;

wherein the switched resistance has a first resistance;

wherein the switching transistor has an on-resistance; and

wherein the on-resistance is at least 20 percent of the total of the first resistance and the on-resistance.

23. The filter of claim 22:

wherein the at least one capacitance network further comprises a plurality of capacitance series connections, the plurality comprising the first capacitance series connection;

wherein each of the plurality of capacitance series connections is connected in parallel with the first non-switched capacitance;

wherein each of the plurality of capacitance series connections comprises a switched capacitance connected in series with a source/drain path of a corresponding switching transistor, the corresponding switching transistor having a gate for receiving a control signal; and

wherein the frequency cutoff point is adjustable in response to the control signals coupled to each switching transistor in the plurality of capacitance series connections.

24. The integrated circuit of claim 23 and further comprising an oscillator, wherein the oscillator comprises a resistor network, the resistor network comprising:

a second non-switched resistance;

a second resistance series connection connected in parallel with the second non-switched resistance, the second resistance series connection comprising a switched resistance connected in series with a source/drain path of a switching transistor, the switching transistor of the second resistance series connection having a gate for receiving a control signal; and

wherein the control signal connected to the gate of the switching transistor in the first resistance series connection is adjusted in response to the control signal connected to the gate of the switching transistor in the second resistance series connection.

25. The integrated circuit of claim 24, wherein the oscillator further comprises a capacitor network, the capacitor network comprising:

a second non-switched capacitance;

a second capacitance series connection connected in parallel with the second non-switched capacitance, the second capacitance series connection comprising a switched capacitance connected in series with a source/drain path of a switching transistor, the switching transistor of the second capacitance series connection having a gate for receiving a control signal; and

wherein the control signal coupled to the gate of the switching transistor in the second capacitance series connection is a complement of the control signal coupled to the gate of the switching transistor in the second resistance series connection.

26. The filter of claim 22:

wherein the at least one resistor network further comprises a plurality of resistance series connections, the plurality comprising the first resistance series connection;

wherein each of the plurality of resistance series connections is connected in parallel with the first non-switched resistance;

wherein each of the plurality of resistance series connections comprises a switched resistance connected in series with a source/drain path of a corresponding switching transistor, the corresponding switching transistor having a gate for receiving a control signal; and

wherein the frequency cutoff point is adjustable in response to the control signals coupled to each switching transistor in the plurality of resistance series connections.

27. The filter of claim 22:

wherein the at least one resistor network comprises a first resistor network coupled between the input node and a first node;

and further comprising;

a second resistor network coupled between the first node and a base of a bipolar junction transistor, the second resistor network comprising;

a second non-switched resistance; and

a second resistance series connection connected in parallel with the second non-switched resistance, the second resistance series connection comprising a switched resistance connected in series with a source/drain path of a switching transistor, the switching transistor having a gate for receiving the control signal.