Apparatus and method for data transmission

• US 20030132926A1
• Filed: 05/07/2002
• Published: 07/17/2003
• Est. Priority Date: 01/14/2002
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Lee, Seok Woo, Song, Jin Kyoung
• Granted Patent: US 7,133,014 B2
• Time in Patent Office: Days
• US Class Current: 345/204
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/06 Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: H04B 15/04 the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder

Abstract

The present invention discloses a data transmission apparatus and method to lower a data transmission voltage for eliminating EMI. In the data driving apparatus, a timing controller aligns input pixel data, lowers input data voltages of the input pixel data, and outputs to a plurality of data transmission lines. A data driver raises the lowered input data voltages for driving the liquid crystal display panel and then converts into analog pixel voltage signals to supply the analog pixel voltage signals to the data lines.

Claims

1. A data transmission apparatus, comprising:

data interfacing means for receiving input data having an input data voltage, lowering the input data voltage, and outputting the lowered input data voltage to a plurality of data transmission lines; and

data input means for raising the lowered data voltage back to the input data voltage for driving a liquid crystal display panel.

2. The data transmission according to claim 1, wherein the input data voltage is lowered by using a voltage-divider.

3. The data transmission apparatus according to claim 1, wherein the voltage-divider includes:

a first resistor arranged in series at each data transmission line; and

a second resistor arranged in parallel at each data transmission line and having a resistance value lower than the first resistor.

4. The data transmission apparatus according to claim 3, wherein the first resistor is arranged at an output terminal of the data interfacing means, and the second resistor is arranged at an input terminal of the data input means.

5. The data transmission apparatus according to claim 3, wherein the first and second resistors are arranged at an output terminal of the data interfacing means.

6. A data transmission method comprising:

lowering an input data voltage of an input data and outputting the lowered input data voltage to a plurality of data transmission lines; and

raising the lowered input voltage of the input data back to the input data voltage for driving a liquid crystal display panel.

7. The method according to claim 6, wherein the input data voltage is lowered by using a voltage-divider.

8. A data driving apparatus of a liquid crystal display for driving a plurality of data lines of a liquid crystal display panel, the apparatus comprising:

a timing controller for aligning input pixel data, for lowering input data voltages of the input pixel data, and for outputting to a plurality of data transmission lines; and

a data driver for raising the lowered input data voltages of the pixel data back to the input data voltages for driving the liquid crystal display panel and converting into analog pixel voltage signals to apply the analog pixel voltage signals to the data lines.

9. The data driving apparatus according to claim 8, wherein the input data voltage is lowered by using a first voltage-divider.

10. The data driving apparatus according to claim 9, wherein the first voltage-divider includes:

a first resistor arranged in series at each data transmission line; and

a second resistor arranged in parallel at each data transmission line and having a resistance value lower than the first resistor.

11. The data driving apparatus according to claim 10, wherein the first resistor is arranged at an output terminal of the timing controller, and the second resistor is arranged at an input terminal of the data driver.

12. The data driving apparatus according to claim 10, wherein the first and second resistors are arranged at an output terminal of the timing controller.

13. The data driving apparatus according to claim 8, wherein the timing controller generates a plurality of control signals for controlling driving of the data driver and lowers voltages of the control signals by using a second voltage-divider to output to a plurality of control signal transmission lines.

14. The data driving apparatus according to claim 13, wherein the second voltage-divider includes:

a first resistor arranged in series at each of the data transmission lines and the control signal transmission lines; and

a second resistor arranged in parallel at each of the data transmission lines and the control signal transmission lines and having a resistance value lower than the first resistor.

15. The data driving apparatus according to claim 14, wherein the first resistor is arranged at an output terminal of the timing controller, and the second resistor is arranged at an input terminal of the data driver.

16. The data driving apparatus according to claim 15, wherein the first resistor is incorporated into the timing controller, and the second resistor is incorporated into the data driver.

17. The data driving apparatus according to claim 14, wherein the first and second resistors are arranged at an output terminal of the timing controller.

18. The data driving apparatus according to claim 17, wherein both the first and second resistors are incorporated into the timing controller.

19. The data driving apparatus according to claim 8, wherein the data driver includes:

a level shifter array for raising the lowered input data voltages of the input pixel data into a primary driving voltage; and

a data-driving unit for converting the raised input data voltages into analog pixel voltage signals to supply the analog pixel voltage signals to the data lines.