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Interconnected high speed electron tunneling devices

  • US 20030133339A1
  • Filed: 01/06/2003
  • Published: 07/17/2003
  • Est. Priority Date: 05/21/2001
  • Status: Active Grant
First Claim
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1. An integrated circuit chip, comprising:

  • a formation of integrated layers, said integrated layers being configured so as to define at least one integrated electronic component, and said integrated layers being further configured to define an integrated electron tunneling device, said integrated electron tunneling device including first and second non-insulating layers spaced apart from one another such that a given voltage can be provided across the first and second non-insulating layers, and an arrangement disposed between the first and second non-insulating layers and configured to serve as a transport of electrons between and to said first and second non-insulating layers, said arrangement including at least a first layer configured such that the transport of electrons includes, at least in part, transport by means of tunneling, wherein said integrated electron tunneling device further includes an antenna structure connected with said first and second non-insulating layers, and wherein said integrated electron tunneling device is electrically connected with said integrated electronic component.

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