SRAM power-up system and method

• US 20030133341A1
• Filed: 01/21/2003
• Published: 07/17/2003
• Est. Priority Date: 12/21/2001
• Status: Active Grant

• Current Assignee: Ken W. Marr
• Original Assignee: Ken W. Marr
• Inventors: Marr, Ken W.
• Granted Patent: US 6,717,866 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Abstract

A power-up circuit for an SRAM, particularly a loadless 4-T SRAM cell having PMOS access transistors. The power-up circuit disables a current path to the digit lines in an array of SRAM cells during power-up of the SRAM. As a result, the SRAM cells cannot draw power from the digit lines during power-up if voltages on word lines in the array during power-up cause access transistors for the SRAM cells to become conductive.

Claims

1. An SRAM cell array, comprising:

an array of SRAM cells arranged in rows and columns, the array including a wordline for each row of the array and a pair of complementary digit lines for each column of the array, each of the SRAM cells having an a pair of access transistors coupled to respective complementary digit lines for a respective column and a gate coupled to a wordline for a respective row; and

a bias circuit coupled to each of the digit lines, the bias circuit being operable to couple a bias current to the digit lines in a normal mode and to couple a voltage to the digit lines that maintains the access transistors non-conductive in a power-up mode.

2. The SRAM cell array of claim 1 wherein the bias circuit comprises:

a respective bias transistor coupled between a supply node and each of the digit lines;

a bias supply transistor coupled between a supply voltage and the supply node of each bias transistor; and

a power-up circuit coupled to a gate of the bias supply transistor, the power-up circuit being operable in a normal mode to couple a voltage to the gate of the bias supply transistor that renders the bias supply transistor conductive, and being operable in the power-up mode to couple a voltage to the gate of the bias supply transistor that renders the bias supply transistor non-conductive.

3. The SRAM cell array of claim 2 wherein each of the SRAM cells comprise a loadless 4-T SRAM cell having PMOS access transistors, wherein the bias supply transistor comprises a PMOS transistor coupled to a positive supply voltage, wherein each of the bias transistors comprise a PMOS transistor, and wherein the power-up circuit is operable to couple substantially ground potential to the gate of the PMOS bias supply transistor in the normal mode and to couple the gate of the PMOS bias supply transistor to substantially the positive supply voltage in the power-up mode.

4. The SRAM cell array of claim 1 wherein the bias circuit comprises:

a respective bias transistor coupled between a supply terminal and each of the digit lines; and

a power-up circuit coupled to the supply terminal of each of the bias transistors, the power-up circuit being operable in a normal mode to couple a supply voltage to the supply terminal of each of the bias transistors, and being operable in the power-up mode isolate the power supply voltage from the supply terminal of each of the bias transistors.

5. The SRAM cell array of claim 4 wherein each of the SRAM cells comprise a loadless 4-T SRAM cell having PMOS access transistors, and wherein each of the bias transistors comprise a PMOS transistor.

6. The SRAM cell array of claim 1 wherein the bias circuit comprises:

a respective bias transistor coupled between a supply voltage and each of the digit lines; and

a power-up circuit coupled to a gate of each of the bias transistors, the power-up circuit receiving a power-up signals and a digit line load signal corresponding to the bias transistors for each pair of complimentary digit lines, the power-up circuit being operable in response to a power-up signal indicative of a normal mode to couple each of the digit line load signals to the gate of the respective bias transistor to renders the bias transistors conductive, and being operable in response to a power-up signal indicative of a power-up mode to couple a voltage to the gate of the bias transistors that renders the bias transistors non-conductive.

7. The SRAM cell array of claim 6 wherein each of the SRAM cells comprise a loadless 4-T SRAM cell having PMOS access transistors, and wherein each of the bias transistors comprise a PMOS transistor.

8. The SRAM cell array of claim 1 wherein the bias circuit comprises:

a respective bias transistor coupled between a supply voltage and each of the digit lines; and

a power-up circuit coupled to a gate of each of the bias transistors, the power-up circuit being operable in a normal mode to apply a voltage to a gate of each of the bias transistors that renders the bias transistors conductive, and being operable in a power-up mode to apply a voltage to the gate of each of the bias transistors that renders the bias transistors non-conductive.

9. The SRAM cell array of claim 8 wherein each of the SRAM cells comprise a loadless 4-T SRAM cell having PMOS access transistors, and wherein each of the bias transistors comprise a PMOS transistor.

10. The SRAM cell array of claim 1 wherein each of the SRAM cells comprise a loadless 4-T SRAM cell having PMOS access transistors, and wherein the bias circuit is operable to couple a positive current to the digit lines in the normal mode and to terminate coupling the positive current from the digit lines in the power-up mode.

14. The SRAM cell array of claim 11 wherein the bias circuit comprises:

a respective bias transistor coupled between a supply terminal and each of the digit lines; and

a power-up circuit coupled to the supply terminal of each of the bias transistors, the power-up circuit being operable in a normal mode to couple a supply voltage to the supply terminal of each of the bias transistors, and being operable in the power-up mode isolate the power supply voltage from the supply terminal of each of the bias transistors.

15. The SRAM cell array of claim 14 wherein each of the SRAM cells comprise a loadless 4-T SRAM cell having PMOS access transistors, and wherein each of the bias transistors comprise a PMOS transistor.

11. An SRAM cell array, comprising:

an array of SRAM cells arranged in rows and columns, each of the SRAM cells including a pair of access switches each having an access terminal and a control terminal;

a wordline coupled to the control terminal of each of the access switches in a respective row;

a pair of complementary digit lines coupled to respective access terminals of each of the access switches in a respective column;

a respective sense amplifier coupled between the complementary digit lines in each of the pairs of complementary digit lines;

a respective write driver coupled between the complementary digit lines in each of the pairs of complementary digit lines;

a respective equilibration switch coupled between the complementary digit lines in each of the pairs of complementary digit lines; and

a bias circuit coupled to each of the digit lines, the bias circuit being operable to couple a bias current to the digit lines in a normal mode and to couple a voltage to the digit lines that maintains the access switches non-conductive in a power-up mode.

12. The SRAM cell array of claim 11 wherein the bias circuit comprises:

a respective bias transistor coupled between a supply node and each of the digit lines;

a bias supply transistor coupled between a supply voltage and the supply node of each bias transistor; and

a power-up circuit coupled to a gate of each of the bias supply transistors, the power-up circuit being operable in a normal mode to couple a voltage to the gate of the bias supply transistor that renders the bias supply transistor conductive, and being operable in the power-up mode to couple a voltage to the gate of the bias supply transistor that renders the bias supply transistor non-conductive.

13. The SRAM cell array of claim 12 wherein each of the access switches comprise PMOS access transistors, wherein each of the SRAM cells comprise a loadless 4-T SRAM cell, wherein each of the bias transistors comprise a PMOS transistor, and wherein the bias supply transistor comprises a PMOS transistor coupled to a positive supply voltage, and wherein the power-up circuit is operable to couple substantially ground potential to the gate of the PMOS bias supply transistors in the normal mode and to couple the gate of the PMOS bias supply transistors to substantially the positive supply voltage in the power-up mode.

16. The SRAM cell array of claim 11 wherein the bias circuit comprises:

a respective bias transistor coupled between a supply voltage and each of the digit lines; and

a power-up circuit coupled to a gate of each of the bias transistors, the power-up circuit receiving a power-up signals and a digit line load signal corresponding to the bias transistors for each pair of complimentary digit lines, the power-up circuit being operable in response to a power-up signal indicative of a normal mode to couple each of the digit line load signals to the gate of the respective bias transistor to renders the bias transistors conductive, and being operable in response to a power-up signal indicative of a power-up mode to couple a voltage to the gate of the bias transistors that renders the bias transistors non-conductive.

17. The SRAM cell array of claim 16 wherein each of the SRAM cells comprise a loadless 4-T SRAM cell having PMOS access transistors, and wherein each of the bias transistors comprise a PMOS transistor.

18. The SRAM cell array of claim 11 wherein the bias circuit comprises:

a respective bias transistor coupled between a supply voltage and each of the digit lines; and

a power-up circuit coupled to a gate of each of the bias transistors, the power-up circuit being operable in a normal mode to apply a voltage to a gate of each of the bias transistors that renders the bias transistors conductive, and being operable in a power-up mode to apply a voltage to the gate of each of the bias transistors that renders the bias transistors non-conductive.

19. The SRAM cell array of claim 18 wherein each of the SRAM cells comprise a loadless 4-T SRAM cell having PMOS access transistors, and wherein each of the bias transistors comprise a PMOS transistor.

20. The SRAM cell array of claim 11 wherein each of the access switches comprise PMOS access transistors, wherein each of the SRAM cells comprise a loadless 4-T SRAM cell, and wherein the bias circuit is operable to couple a positive supply current to the digit lines in the normal mode and to terminate coupling the positive current from the digit lines in the power-up mode.

21. The SRAM cell array of claim 11 wherein each of the access switches comprise a transistor, the access terminal for each of the access switches comprises a drain or a source of the access transistor, and the control terminal for each of the access switches comprises a gate of the access transistor.

22. A static random access memory (“

SRAM”

) comprising;

an address bus;

a control bus;

a data bus;

an address decoder coupled to the address bus;

a read/write circuit coupled to the data bus;

a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;

the memory-cell array comprising;

an array of SRAM cells arranged in rows and columns, each of the SRAM cells including a pair of access switches each having an access terminal and a control terminal;

a wordline coupled to the control terminal of each of the access switches in a respective row;

a pair of complementary digit lines coupled to respective access terminals of each of the access switches in a respective column;

a respective sense amplifier coupled between the complementary digit lines in each of the pairs of complementary digit lines;

a respective write driver coupled between the complementary digit lines in each of the pairs of complementary digit lines; and

a respective equilibration switch coupled between the complementary digit lines in each of the pairs of complementary digit lines;

a bias circuit coupled to each of the digit lines, the bias circuit being operable to couple a bias current to the digit lines in a normal mode and to couple a voltage to the digit lines that maintains the access switches non-conductive in a power-up mode; and

a control circuit operable to control the operation of the SRAM.

23. The SRAM of claim 22 wherein the bias circuit comprises:

a respective bias transistor coupled between a supply node and each of the digit lines;

a bias supply transistor coupled between a supply voltage and the supply node of each bias transistor; and

a power-up circuit coupled to a gate of the supply bias transistor, the power-up circuit being operable in a normal mode to couple a voltage to the gate of the bias supply transistor that renders the bias supply transistor conductive, and being operable in the power-up mode to couple a voltage to the gate of the bias supply transistor that renders the bias supply transistor non-conductive.

24. The SRAM of claim 23 wherein the bias supply transistor comprises a PMOS transistor coupled to a positive supply voltage, wherein each of the access switches comprise PMOS access transistors, wherein each of the SRAM cells comprise a loadless 4-T SRAM cell, wherein each of the bias transistors comprise a PMOS transistor, and wherein the power-up circuit is operable to couple substantially ground potential to the gate of the PMOS bias supply transistor in the normal mode and to couple the gate of the PMOS bias supply transistor to substantially the positive supply voltage in the power-up mode.

25. The SRAM of claim 22 wherein the bias circuit comprises:

a respective bias transistor coupled between a supply terminal and each of the digit lines; and

a power-up circuit coupled to the supply terminal of each of the bias transistors, the power-up circuit being operable in a normal mode to couple a supply voltage from the positive supply voltage to the supply terminal of each of the bias transistors, and being operable in the power-up mode isolate the power supply voltage from the supply terminal of each of the bias transistors.

26. The SRAM of claim 25 wherein each of the SRAM cells comprise a loadless 4-T SRAM cell having PMOS access transistors, and wherein each of the bias transistors comprise a PMOS transistor.

27. The SRAM of claim 22 wherein the bias circuit comprises:

a respective bias transistor coupled between a supply voltage and each of the digit lines; and

a power-up circuit coupled to a gate of each of the bias transistors, the power-up circuit receiving a power-up signals and a digit line load signal corresponding to the bias transistors for each pair of complimentary digit lines, the power-up circuit being operable in response to a power-up signal indicative of a normal mode to couple each of the digit line load signals to the gate of the respective bias transistor to renders the bias transistors conductive, and being operable in response to a power-up signal indicative of a power-up mode to couple a voltage to the gate of the bias transistors that renders the bias transistors non-conductive.

28. The SRAM of claim 27 wherein each of the SRAM cells comprise a loadless 4-T SRAM cell having PMOS access transistors, and wherein each of the bias transistors comprise a PMOS transistor.

29. The SRAM of claim 22 wherein the bias circuit comprises:

a respective bias transistor coupled between a supply voltage and each of the digit lines; and

a power-up circuit coupled to a gate of each of the bias transistors, the power-up circuit being operable in a normal mode to apply a voltage to a gate of each of the bias transistors that renders the bias transistors conductive, and being operable in a power-up mode to apply a voltage to the gate of each of the bias transistors that renders the bias transistors non-conductive.

30. The SRAM of claim 29 wherein each of the SRAM cells comprise a loadless 4-T SRAM cell having PMOS access transistors, and wherein each of the bias transistors comprise a PMOS transistor.

31. The SRAM of claim 22 wherein each of the access switches comprise PMOS access transistors, wherein each of the SRAM cells comprise a loadless 4-T SRAM cell, and wherein the bias circuit is operable to couple a positive current to the digit lines in the normal mode and to terminate coupling the positive current from the digit lines in the power-up mode.

32. The SRAM of claim 22 wherein each of the access switches comprise a transistor, the access terminal for each of the access switches comprises a drain or a source of the access transistor, and the control terminal for each of the access switches comprises a gate of the access transistor.

33. The SRAM of claim 22, wherein the SRAM comprises a synchronous SRAM.

34. A computer system, comprising:

a processor having a processor bus;

at least one input device coupled to the processor through the processor bus;

at least one output device coupled to the processor through the processor bus;

at least one data storage devices coupled to the processor through the processor bus

a system memory coupled to the processor through the processor bus; and

an static random access cache memory coupled to the processor through the processor bus, the static random access cache memory comprising;

an address bus;

a control bus;

a data bus;

an address decoder coupled to the address bus;

a read/write circuit coupled to the data bus;

a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;

the memory-cell array comprising;

an array of SRAM cells arranged in rows and columns, each of the SRAM cells including a pair of access switches each having an access terminal and a control terminal;

a wordline coupled to the control terminal of each of the access switches in a respective row;

a pair of complementary digit lines coupled to respective access terminals of each of the access switches in a respective column;

a respective sense amplifier coupled between the complementary digit lines in each of the pairs of complementary digit lines;

a respective write driver coupled between the complementary digit lines in each of the pairs of complementary digit lines; and

a respective equilibration switch coupled between the complementary digit lines in each of the pairs of complementary digit lines;

a bias circuit coupled to each of the digit lines, the bias circuit being operable to couple a bias current to the digit lines in a normal mode and to couple a voltage to the digit lines that maintains the access switches non-conductive in a power-up mode; and

a control circuit operable to control the operation of the SRAM.

35. The computer system of claim 34 wherein the bias circuit comprises:

a respective bias transistor coupled between a supply node and each of the digit lines;

a bias supply transistor coupled between a supply voltage and the supply node of each bias transistor; and

a power-up circuit coupled to a gate of the bias transistor, the power-up circuit being operable in a normal mode to couple a voltage to the gate of the bias supply transistor that renders the bias supply transistor conductive, and being operable in the power-up mode to couple a voltage to the gate of the bias supply transistor that renders the bias supply transistor non-conductive.

36. The computer system of claim 35 wherein the bias supply transistor comprises a PMOS transistor coupled to a positive supply voltage, wherein each of the access switches comprise PMOS access transistors, wherein each of the SRAM cells comprise a loadless 4-T SRAM cell, wherein each of the bias transistors comprise a PMOS transistor, and wherein the power-up circuit is operable to couple substantially ground potential to the gate of the PMOS bias supply transistor in the normal mode and to couple the gate of the PMOS bias supply transistor to substantially the positive supply voltage in the power-up mode.

37. The computer system of claim 34 wherein the bias circuit comprises:

a respective bias transistor coupled between a supply terminal and each of the digit lines; and

a power-up circuit coupled to the supply terminal of each of the bias transistors, the power-up circuit being operable in a normal mode to couple a supply voltage from the positive supply voltage to the supply terminal of each of the bias transistors, and being operable in the power-up mode isolate the power supply voltage from the supply terminal of each of the bias transistors.

38. The computer system of claim 37 wherein each of the SRAM cells comprise a loadless 4-T SRAM cell having PMOS access transistors, and wherein each of the bias transistors comprise a PMOS transistor.

39. The computer system of claim 34 wherein the bias circuit comprises:

a respective bias transistor coupled between a supply voltage and each of the digit lines; and

a power-up circuit coupled to a gate of each of the bias transistors, the power-up circuit receiving a power-up signals and a digit line load signal corresponding to the bias transistors for each pair of complimentary digit lines, the power-up circuit being operable in response to a power-up signal indicative of a normal mode to couple each of the digit line load signals to the gate of the respective bias transistor to renders the bias transistors conductive, and being operable in response to a power-up signal indicative of a power-up mode to couple a voltage to the gate of the bias transistors that renders the bias transistors non-conductive.

40. The computer system of claim 39 wherein each of the SRAM cells comprise a loadless 4-T SRAM cell having PMOS access transistors, and wherein each of the bias transistors comprise a PMOS transistor.

41. The computer system of claim 34 wherein the bias circuit comprises:

a respective bias transistor coupled between a supply voltage and each of the digit lines; and

a power-up circuit coupled to a gate of each of the bias transistors, the power-up circuit being operable in a normal mode to apply a voltage to a gate of each of the bias transistors that renders the bias transistors conductive, and being operable in a power-up mode to apply a voltage to the gate of each of the bias transistors that renders the bias transistors non-conductive.

42. The computer system of claim 41 wherein each of the SRAM cells comprise a loadless 4-T SRAM cell having PMOS access transistors, and wherein each of the bias transistors comprise a PMOS transistor.

43. The computer system of claim 34 wherein each of the access switches comprise PMOS access transistors, wherein each of the SRAM cells comprise a loadless 4-T SRAM cell, and wherein the bias circuit is operable to couple a positive current to the digit lines in the normal mode and to terminate coupling the positive current from the digit lines in the power-up mode.

44. The computer system of claim 34 wherein each of the access switches comprise a transistor, the access terminal for each of the access switches comprises a drain or a source of the access transistor, and the control terminal for each of the access switches comprises a gate of the access transistor.

45. The computer system of claim 34, wherein the SRAM comprises a synchronous SRAM.

46. In an array of SRAM cells arranged in rows and columns and having a pair of complementary digit lines for each column of the array coupled to respective access transistors for each SRAM cell, a method of controlling the power-up current drawn by the array, comprising:

applying a predetermined bias current to the digit lines in a normal mode; and

coupling the digit lines to a voltage that maintains the access transistors non-conductive in a power-up mode.

47. The method of claim 46 wherein a respective bias transistor is coupled between a supply node and each of the digit lines, and wherein the act of biasing the digit lines to a predetermined bias voltage in a normal mode comprises coupling a voltage to the gate of the bias transistor that renders the bias transistor conductive during the normal mode.

48. The method of claim 46 wherein a respective bias transistor is coupled between a supply node and each of the digit lines, and wherein the act of coupling the digit lines to a voltage that maintains the access transistors non-conductive in a power-up mode comprises coupling a voltage to the gate of the bias transistor that renders the bias transistor non-conductive in the power-up mode.

49. The method of claim 46 wherein a respective bias transistor is coupled between a supply voltage and each of the digit lines, wherein the act of biasing the digit lines to a predetermined bias voltage in a normal mode comprises coupling a voltage to the gate of the bias transistor that renders the bias transistor conductive during the normal mode, and wherein the act of coupling the digit lines to a voltage that maintains the access transistors non-conductive in a power-up mode comprises coupling a voltage to the gate of the bias transistor that renders the bias transistor non-conductive in the power-up mode.

50. The method of claim 49 wherein each of the SRAM cells comprise a loadless 4-T SRAM cell having PMOS access transistors, wherein each of the bias transistor comprises a PMOS transistor coupled to a positive supply voltage, wherein the act of coupling a voltage to the gate of the bias transistor that renders the bias transistor conductive during the normal mode comprises coupling substantially ground potential to the gate of the PMOS bias transistor in the normal mode, and wherein the act of coupling a voltage to the gate of the bias transistor that renders the bias transistor non-conductive in the power-up mode comprises coupling the gate of the PMOS bias transistor to substantially the positive supply voltage in the power-up mode.

51. The method of claim 46, wherein a respective bias transistor is coupled between a supply terminal and each of the digit lines, and wherein the act of biasing the digit lines to a predetermined bias voltage in-a normal mode comprises coupling a supply voltage from the supply terminal each of the bias transistors.

52. The method of claim 51, wherein a respective bias transistor is coupled between a supply terminal and each of the digit lines, and wherein the act of coupling the digit lines to a voltage that maintains the access transistors non-conductive in a power-up mode comprises isolating the supply voltage from the supply terminal of each of the bias transistors.

53. The method of claim 46, wherein a respective bias transistor is coupled between a supply terminal and each of the digit lines, wherein the act of applying a predetermined bias current to the digit lines in a normal mode comprises coupling a supply voltage from the supply terminal each of the bias transistors, and wherein the act of coupling the digit lines to a voltage that maintains the access transistors non-conductive in a power-up mode comprises isolating the supply voltage from the supply terminal of each of the bias transistors.