Semiconductor memory device

• US 20030133346A1
• Filed: 01/07/2003
• Published: 07/17/2003
• Est. Priority Date: 01/11/2002
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Honda, Yasuhiko
• Granted Patent: US 6,813,207 B2
• Time in Patent Office: Days
• US Class Current: 365/205
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits

Abstract

A semiconductor memory device comprises a plurality of sense amplifiers divided into a plurality of groups, each of the groups being a unit of a page readout operation; a sense amplifier control signal generation circuit which outputs a sense amplifier control signal for enabling the sense amplifiers of each group and disabling the sense amplifiers of each group, wherein the sense amplifier control signal enables and disables the sense amplifiers of a part of the groups at different timing from the sense amplifiers of other groups; and a plurality of memory cells connected to the sense amplifiers via data lines.

Claims

1. A semiconductor memory device, comprising:

a plurality of sense amplifiers divided into a plurality of groups, each of the groups being a unit of a page readout operation;

a sense amplifier control signal generation circuit which outputs a sense amplifier control signal for enabling the sense amplifiers of each group and disabling the sense amplifiers of each group, wherein the sense amplifier control signal enables and disables the sense amplifiers of a part of the groups at different timing from the sense amplifiers of other groups; and

a plurality of memory cells connected to the sense amplifiers via data lines.

2. The semiconductor memory device as set forth in claim 1, wherein the sense amplifier control signal generation circuit outputs the sense amplifier control signal so as to enable the sense amplifiers of each group at different timing and disable the sense amplifiers of each group at different timing.

3. The semiconductor memory device as set forth in claim 2, wherein the sense amplifier control signal generation circuit enables the sense amplifiers of the group which corresponds to an inputted address signal and then sequentially enables the sense amplifiers of the other groups.

4. The semiconductor memory device as set forth in claim 2, wherein a period from enabling the sense amplifiers to disabling them in accordance with the sense amplifier control signal is a time necessary for precharging the data lines connected to the memory cells, determining data read out from the memory cells via the data lines, and latching the data.

5. The semiconductor memory device as set forth in claim 4, wherein the sense amplifier control signal generation circuit comprises sense amplifier enable signal generation circuits for every group, and each of the sense amplifier enable signal generation circuits outputs the sense amplifier control signal.

6. The semiconductor memory device as set forth in claim 5, wherein each of the sense amplifier enable signal generation circuits comprises:

a first generation circuit which generates a data line precharge signal for precharging the data lines in accordance with an inputted trigger signal;

a second generation circuit which generates a sense signal for reading out data from the memory cells via the data lines and determining the data in accordance with the data line precharge signal;

a third generation circuit which generates a data latch signal for latching the determined data in accordance with the sense signal; and

a fourth generation circuit which generates the sense amplifier control signal of an enable state while the data line precharge signal, the sense signal and the data latch signal are outputted.

7. The semiconductor memory device as set forth in claim 6, wherein the sense amplifier control signal generation circuit further comprises:

an address decode circuit which decodes the inputted address signal and outputs a first group selection signal for firstly enabling the sense amplifier of the group which corresponds to the decoded address signal;

an increment circuit which outputs the trigger signal into the sense amplifier enable signal generation circuit of the group which corresponds to the decoded address signal in accordance with the first group selection signal and sequentially outputs the trigger signal into the sense amplifier enable signal generation circuit of the other groups.

8. The semiconductor memory device as set forth in claim 7, wherein the increment circuit sequentially outputs the trigger signal by an increment operation which synchronizes with a first clock signal generated inside the semiconductor memory device.

9. The semiconductor memory device as set forth in claim 8, wherein the increment circuit sequentially outputs the trigger signal in a cycle of a half period of the first clock signal, by an increment operation which synchronizes with the first clock signal and a second clock signal which is shifted a half period with respect to the first clock signal.

10. The semiconductor memory device as set forth in claim 9, wherein a clock frequency of the first clock signal is changed in accordance with a readout mode which is selected by an input signal from the outside of the semiconductor memory device.