ACTIVE MATRIX THIN FILM TRANSISTOR ARRAY BACKPLANE
First Claim
1. A method of fabricating a thin film transistor active matrix backplane, comprising the steps of:
- depositing a first passivation layer on a polyimide substrate to passivate the substrate;
applying a gate material to the first passivation layer;
patterning the gate material to form an array of gate electrodes;
depositing a gate insulating layer over the gate electrodes and the first passivation layer;
depositing a channel layer comprising amorphous silicon over the gate insulating layer;
depositing a contact layer comprising phosphorus doped amorphous silicon on the semiconducting channel layer;
depositing a source-drain layer on the contact layer;
patterning an array of source electrodes, drain electrodes, lines and pads in the source-drain layer;
patterning an array of transistor islands on the source and drain electrodes;
depositing a protective layer on the source-drain layer; and
exposing the drain electrodes and pads.
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Accused Products
Abstract
A thin film transistor array fabricated on a polyimide substrate forms a backplane for an electronic display. The thin film transistor array incorporates gate electrodes, a gate insulating layer, semiconducting channel layers deposited on top of the gate insulating layer, a source electrode, a drain electrode and a contact layer beneath each of the source and drain electrodes and in contact with at least the channel layer. An insulating encapsulation layer is positioned on the channel layer. The layers are deposited onto the polyimide substrate using PECVD and etched using photolithography to form the backplane.
82 Citations
95 Claims
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1. A method of fabricating a thin film transistor active matrix backplane, comprising the steps of:
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depositing a first passivation layer on a polyimide substrate to passivate the substrate; applying a gate material to the first passivation layer; patterning the gate material to form an array of gate electrodes; depositing a gate insulating layer over the gate electrodes and the first passivation layer; depositing a channel layer comprising amorphous silicon over the gate insulating layer; depositing a contact layer comprising phosphorus doped amorphous silicon on the semiconducting channel layer; depositing a source-drain layer on the contact layer; patterning an array of source electrodes, drain electrodes, lines and pads in the source-drain layer; patterning an array of transistor islands on the source and drain electrodes; depositing a protective layer on the source-drain layer; and exposing the drain electrodes and pads. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 93, 94, 95)
washing the polyimide substrate; and exposing the polyimide substrate to a plasma.
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6. The method of claim 1, wherein the passivation layer comprises SiNx.
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7. The method of claim 6, wherein the step of depositing the passivation layer comprises using a gas mixture of H2, SiH4 and NH3 at about 150 º
- C at about 0.5 Torr and about 0.067 Watts per centimeter squared.
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8. The method of claim 7, wherein the passivation layer has a thickness of between about 250 nanometers and about 1000 nanometers.
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9. The method of claim 1, further comprising the step of depositing a second passivation layer on a bottom surface of the polyimide substrate.
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10. The method of claim 1, wherein the gate material comprises a first layer of a first metal and a second layer of a second metal overlying the first layer.
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11. The method of claim 10, wherein the first metal in the gate material is aluminum and the second metal is chromium.
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12. The method of claim 10, wherein the first metal in the gate material is titanium and the second metal is chromium.
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13. The method of claim 10, wherein the first layer of the gate materiel is between about 500 angstroms and about 2000 angstroms thick and the second layer of the gate material is between about 50 angstroms and about 200 angstroms thick.
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14. The method of claim 1, wherein the step of patterning the gate material to form an array of gate electrodes comprises providing a first mask and aligning the mask with the polyimide substrate and an array of gate electrode features and gate line features.
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15. The method of claim 14, wherein the step of patterning the gate material further comprises the photolithographic steps of:
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spin coating the sample with an adhesive promoter; applying photoresist layer; heating the sample; etching the gate material; and removing the photoresist.
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16. The method of claim 1, wherein the step of depositing the gate insulating layer comprises using plasma enhanced chemical vapor deposition techniques.
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17. The method of claim 16, wherein the gate insulating layer comprises SiNx.
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18. The method of claim 16, wherein the step of depositing the gate insulating layer uses a gas mixture of H2, SiH4 and NH3 at about 150 º
- C at about 0.5 Torr and about 0.067 Watts per centimeter squared.
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19. The method of claim 18, wherein the gate insulating layer has a thickness of between about 1800 angstroms and about 7200 angstroms.
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20. The method of claim 1, wherein the step of depositing the amorphous silicon semiconducting channel layer uses a mixture of SiH4 and H2 at about 150 º
- C at about 0.5 Torr and about 0.027 Watts per centimeter squared.
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21. The method of claim 20, wherein the channel layer has a thickness of between about 1000 angstroms and about 4000 angstroms.
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22. The method of claim 1, wherein the step of depositing the contact layer uses a mixture of SiH4 at about 44 sscm and PH3 at about 6 sscm at about 0.5 Torr and about 0.018 Watts per centimeter squared.
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23. The method of claim 22, wherein the contact layer has a thickness of between about 250 angstroms and about 1000 angstroms.
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24. The method of claim 1, wherein the source-drain layer comprises aluminum.
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25. The method of claim 1, wherein the source drain layer comprises a first layer of a first metal, a second layer of a second metal overlying the first layer, and a third layer of a third metal overlying the second layer.
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26. The method of claim 25, wherein the first metal in the source drain material is chromium, the second metal is aluminum and the third layer is chromium.
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27. The method of claim 25, wherein the first layer of the source-drain material is about 100 angstroms thick and the second layer of the gate material is about 1000 angstroms thick and the third layer is about 100 angstroms thick.
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28. The method of claim 1, wherein the step of depositing one of the source-drain and the gate metal layer comprises using one of an e-beam evaporator and a thermal evaporator.
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29. The method of claim 1, wherein the step of patterning the array of source electrodes, drain electrodes, lines and pads in the source-drain layer comprises using a second mask having alignment marks and an array of source electrode features, drain electrode features, line features and pad features.
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30. The method of claim 29, wherein the source-drain layer is patterned using a contact aligner.
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31. The method of claim 29, wherein the step of patterning the source-drain material further comprises the photolithographic steps of:
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spin coating the sample with an adhesive promoter; applying a photoresist layer; heating the sample; etching the source and drain electrodes, lines and pads; heating the sample; dry etching the contact layer with a plasma etcher using CF4, removing the photoresist.
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32. The method of claim 1, wherein the step of patterning the transistor islands comprises the steps of providing a third mask and using a photolithography technique to pattern the island.
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33. The method of claim 32, wherein the step of patterning the channel material to form the transistor islands further comprises:
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spin coating the sample with an adhesive promoter; applying photoresist; heating the sample; etching the channel layer with a plasma etcher using CF4; and removing the photoresist.
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34. The method of claim 1, wherein the step of depositing the protective layer comprises using a plasma enhanced chemical vapor deposition technique.
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35. The method of claim 34, wherein the protective layer comprises SiNx.
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36. The method of claim 35, wherein the step of depositing the protective layer comprises using a gas mixture of H2, SiH4 and NH3 at about 150 º
- C at 0.5 Torr and 0.067 Watts per centimeter squared.
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37. The method of claim 36, wherein the protective layer has a thickness of about 2600 Angstroms.
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38. The method of claim 36, wherein the step of patterning the protective layer further comprises:
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spin coating the sample with an adhesive promoter; applying photoresist layer; heating the sample; dry etching the protective with a plasma etcher using CF4 and O2; and removing the photoresist.
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39. The method of claim 1, wherein the step of exposing the drain electrodes and pads comprises employing a reactive ion etching technique to remove a portion of the gate insulating layer and the protective layer.
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40. The method of claim 2, wherein the step of annealing has a duration of about one hour at a temperature of about 195º
- C and wherein the forming gas is 15 % H2 in N2.
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93. The portable electronic device of claim 44, wherein a portion of the display assembly is formed in accordance with the method of claim 1.
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94. The flexible electronic display of claim 57, wherein the one or more
thin film transistors is formed in accordance with the method of claim 1. -
95. The display device of claim 74, wherein a portion of the plurality of pixels and the matrix of transistors are formed in accordance with the method of claim 1.
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41. A polymer dispersed electronic display comprising:
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a backplane having an active matrix thin film transistor array formed on a flexible polyimide substrate; a top layer of indium tin oxide coated polyester; and a middle layer disposed between the backplane and the top layer composed of a 20;
80 mixture of prepolymer PN393 and TL213;wherein the middle layer is cured using a light source.
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42. A method of making a polymer dispersed electronic display, comprising the steps of:
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forming an active matrix thin film transistor array backplane on a polyimide substrate; depositing a display medium on the active matrix thin film transistor array backplane; depositing a protective layer comprising indium tin oxide coated polyester over the display medium; and curing the display medium between the backplane and the protective layer.
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43. A thin film transistor backplane, comprising:
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a polyimide substrate; a first passivation layer deposited on a deposition surface of the polyimide substrate; an array of gate electrodes and gate lines patterned on the passivation layer; a gate insulating layer deposited over the array of gate electrodes and gate lines;
a semiconducting channel layer deposited over the gate insulating layer;a contact layer deposited on and in contact with the channel layer; and an array of source electrodes, drain electrodes, lines and pads fabricated on and in contact with the contact layer.
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44. A portable electronic device comprising,
a housing to house a portion of one or more components of said portable electronic device; - and
a display assembly coupled to a flexible backplane assembly having formed thereon one or more transistors for displaying content to a user of the portable electronic device, the flexible backplane assembly capable of flexing in one or more dimensions to change a topography of a surface of the flexible backplane assembly, and wherein a portion of the display assembly forms a portion of the housing. - View Dependent Claims (45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56)
a flexible display medium, and a flexible layer of transparent material disposed over a portion of the flexible display medium. -
48. The portable electronic device of claim 44, wherein the housing comprises, a moveable member moveable from a first position to a second position to access a portion of the portable electronic device.
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49. The portable electronic device of claim 47, wherein the flexible display medium comprises, a bi-stable, non-volatile display medium.
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50. The portable electronic device of claim 49, wherein the flexible display medium comprises,
electrophoretic material having a pattern of addressable pixel locations; - and
an activation grid for supplying a charge to selected addressable pixel locations to form the content for displaying to the user.
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51. The portable electronic device of claim 49, wherein the flexible display medium comprises at least one of a plurality of bichromal spheres, a plurality of pneumatic liquid crystals, a plurality of cholesteric liquid crystals, and a plurality of chiral compounds.
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52. The portable electronic device of claim 45, wherein the flexible display assembly is capable of having a first portion of the surface of the flexible display assembly flex to conform to a first radius and a second portion of the surface of the flexible display assembly flex to conform to a second radius.
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53. The portable electronic device of claim 44, wherein the portable electronic device comprises at least one of, a personal digital assistant (PDA), a cell phone, a timepiece, and a mobile electronic device associated with a network.
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54. The portable electronic device of claim 47, wherein the flexible display medium comprises a volatile medium.
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55. The portable electronic device of claim 54, wherein the volatile medium comprises at least one of, an organic light emitting diode, a liquid crystal, and a polymer dispersed liquid crystal.
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56. The portable electronic device of claim 47, wherein the flexible display medium comprises a medium that includes at least one of a surface stabilized ferroelectric liquid crystal, a fast multi stable liquid crystal, and OYNXTM chemical substance.
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57. A flexible electronic display having a plurality of pixels, the flexible electronic display comprising,
a flexible display medium with a transparent reference electrode layer for displaying indicia to an operator, the indicia providing the operator with indications of a state of a monitored process; - and
one or more thin film transistors coupled to the flexible display medium and formed on a substrate capable of flexing in a plurality of dimensions, the one or more thin film transistors and the flexible display medium flex to adapt to one or more contours of a surface of the instrument panel during mounting of said flexible electronic display thereto. - View Dependent Claims (58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 89, 90)
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74. A display device for displaying content to a user, said display device comprising,
a matrix of transistors formed on a flexible substrate, the flexible substrate capable of flexing in one or more dimensions with the transistors formed thereon to adapt to a desired contour, and a plurality of pixels coupled to the matrix of transistors, each of the plurality of pixels addressable by the matrix of transistors to transfer a change from a selected one of the matrix of transistors to one of the plurality of pixels to display a portion of the content to the user.
Specification