Two level multi-tier system bus
First Claim
1. Apparatus for managing flow of information among plural processors of a processing array, comprising:
- a system bus for interconnecting at least two processors; and
means for arbitrating access to at least a first portion of a system bus among said at least two processors to transfer information over said first portion, said information being transferred using a protocol by which a system bus performs control actions for system bus access independently of said at least two processors.
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Abstract
The present invention is directed to a method and apparatus utilizing a two-level, multi-tier system bus. The multi-tier system bus of the present invention allows for the flow of information to be managed among plural processors by connecting processors within modules on a local bus, which is then connected to the system bus by way of a gateway. A system controller and arbitrator is provided for arbitrating access to the system bus by the various modules. The present invention, by way of the system controller initiates and performs control actions and allows the system bus to be freed from transmission delays of prior approaches associated with transmitting data packets. The present invention accomplishes this by establishing a clear path segment between various modules or devices contained on the system bus, and processors contained within modules located on local buses such that delays associated with transmission of such data packets is greatly reduced, and processing speeds and rates are greatly increased. The present invention also avoids the complications of software arbitration, as all of the arbitration of the present invention is accomplished by hardware.
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Citations
31 Claims
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1. Apparatus for managing flow of information among plural processors of a processing array, comprising:
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a system bus for interconnecting at least two processors; and
means for arbitrating access to at least a first portion of a system bus among said at least two processors to transfer information over said first portion, said information being transferred using a protocol by which a system bus performs control actions for system bus access independently of said at least two processors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method for managing the flow of information among plural processors of a processing array, comprising the steps of:
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interconnecting at least two processors by a system bus; and
arbitrating access to at least a first portion of a system bus among said at least two processors to transfer information over said first portion, said information being transferred using a protocol by which a system bus performs control actions for system bus access independently of said at least two processors. - View Dependent Claims (18, 19, 28, 29, 30, 31)
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20. The method of step 19, wherein said steps of requesting and receiving are accomplished by a device connected to the system bus.
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21. The method of step 20, wherein said bus grant signal is issued by a system bus arbitration unit.
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22. The method of step 17, wherein said step of arbitrating comprises the steps of:
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inquiring if the system bus is in use;
verifying that a destination device is not busy once the system bus is not muse;
requesting access to the system bus to a system bus arbitration unit;
gaining access to the system bus from said system bus arbitration unit; and
transmitting data packets to said destination device.
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23. The method of step 22, wherein the system bus arbitration unit allows continual access to the system bus if the destination device does not become busy, if the bus does not become busy, and if no other device requests access to the system bus.
- 24. The method of step 23, wherein the system bus arbitration unit grants access to a second device upon request during a transmission of a data packet by another device on the system bus.
Specification