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Two level multi-tier system bus

  • US 20030135678A1
  • Filed: 09/20/2001
  • Published: 07/17/2003
  • Est. Priority Date: 09/20/2001
  • Status: Active Grant
First Claim
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1. Apparatus for managing flow of information among plural processors of a processing array, comprising:

  • a system bus for interconnecting at least two processors; and

    means for arbitrating access to at least a first portion of a system bus among said at least two processors to transfer information over said first portion, said information being transferred using a protocol by which a system bus performs control actions for system bus access independently of said at least two processors.

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