Novel personal electronics device with a dual core processor

• US 20030135771A1
• Filed: 02/28/2003
• Published: 07/17/2003
• Est. Priority Date: 03/16/2001
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Dualcor Technologies Incorporated
• Inventors: Cupps, Bryan T., Glass, Timothy J.
• Granted Patent: US 7,231,531 B2
• Time in Patent Office: Days
• US Class Current: 713/320
• CPC Class Codes: G06F 1/1626 with a single-body enclosure integrating a flat display, e.g. Personal Digital Assistants [PDAs]
• CPC Class Codes: G06F 1/1632 External expansion units, e.g. docking stations
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 2209/509 Offload
• CPC Class Codes: G06F 3/04886 by partitioning the display area of the touch-screen or the surface of the digitising tablet into independently controllable areas, e.g. virtual keyboards or menus
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals
• CPC Class Codes: G06F 9/5044 considering hardware capabilities
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: H04L 12/2803 Home automation networks
• CPC Class Codes: H04M 1/271 controlled by voice recognition
• CPC Class Codes: H04M 1/72403 with means for local support of applications that increase the functionality
• CPC Class Codes: H04M 1/72409 by interfacing with external accessories hands-free H04M1/60
• CPC Class Codes: H04M 1/72412 using two-way short-range wireless interfaces
• CPC Class Codes: H04M 1/72415 for remote control of appliances
• CPC Class Codes: H04M 2250/02 including a Bluetooth interface
• CPC Class Codes: H04M 2250/12 including a sensor for measuring a physical value, e.g. temperature or motion telephones including GPS signal receivers H04M2250/10
• CPC Class Codes: H04W 52/027 : by controlling a display operation or backlight unit
• CPC Class Codes: H04W 52/028 : switching on or off only a part of the equipment circuit blocks
• CPC Class Codes: H04W 52/029 : reducing the clock frequency of the controller
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/70 : in wireless communication networks

Abstract

A novel personal electronic device includes a processor having first (embedded) and second (non-embedded) cores including associated operating systems and functions. In one aspect, the first core performs relatively limited functions, while the second core performs relatively broader functions under control of the first core. Often the second core requires more power than the first core and is selectively operated by the first core to minimize overall power consumption. Protocols for functions to be performed by the second core may be provided directly to the second core and processed by the second core. In another aspect, a display controller is designed to interface with both cores. In another aspect, the operating systems work with one another. In another aspect, the first core employs a thermal control program. Advantages of the invention include a broad array of functions performed by a relatively small personal electronics device.

Claims

1. A personal electronics device comprising:

a processor having a non-embedded core configured to perform a set of functions, and an embedded core configured to perform a limited set of functions compared to the non-embedded core and configured to control operation of the non-embedded core;

a display coupled to the processor and configured to selectively display information from the embedded processor and the non-embedded processor; and

an input device coupled to the embedded processor and non-embedded processor to allow a user to provide instructions to the embedded processor and non-embedded processor.

2. The personal electronics device of claim 1, wherein the embedded core and non-embedded core are configured to selectively operate simultaneously.

3. The personal electronics device of claim 1, wherein the instructions provided by the user include an instruction to simultaneously operate the embedded processor and non-embedded cores.

4. The personal electronics device of claim 1, wherein the embedded core controls the non-embedded core.

5. The personal electronics device of claim 2, wherein the embedded core controls the non-embedded core.

6. The personal electronics device of claim 4, further comprising:

a heat sensitive circuit coupled to the embedded processor and configured to generate a heat signal; and

wherein the embedded core controls the clock rate of the non-embedded core based at least in part on the heat signal.

7. The personal electronics device of claim 5, further comprising:

a heat sensitive circuit coupled to the embedded processor and configured to generate a heat signal; and

wherein the embedded core is configured to control the clock rate of the non-embedded core based at least in part on the heat signal.

8. The personal electronics device of claim 1, wherein the processor includes a shared display circuit coupled to the embedded core and the non-embedded core and configured to normalize the display output.

9. The personal electronics device of claim 2, wherein the processor includes a shared display circuit coupled to the embedded core and the non-embedded core and configured to normalize the display output.

10. The personal electronics device of claim 4, wherein the processor includes a shared display circuit coupled to the embedded core and the non-embedded core and configured to normalize the display output.

11. A processor comprising:

a non-embedded core configured to perform a set of functions; and

an embedded core configured to perform a limited set of functions compared to the non-embedded core and configured to control operation of the non-embedded core.

12. The processor of claim 11, wherein the embedded core and non-embedded core are configured to selectively operate simultaneously.

13. The processor of claim 11, wherein the embedded core controls the non-embedded core.

14. The processor of claim 12, wherein the embedded core controls the non-embedded core.

15. The processor of claim 13, wherein:

the embedded core includes a heat signal input; and

the embedded core is configured to control the clock rate of the non-embedded core based at least in part on the heat signal.

16. The processor claim 11, further comprising a shared display circuit coupled to the embedded core and the non-embedded core and configured to normalize the display output.

17. The processor claim 12, further comprising a shared display circuit coupled to the embedded core and the non-embedded core and configured to normalize the display output.

18. The processor claim 13, further comprising a shared display circuit coupled to the embedded core and the non-embedded core and configured to normalize the display output.

19. A method of operating a processor having a non-embedded core configured to perform a set of functions;

and an embedded core configured to perform a limited set of functions compared to the non-embedded core, comprising the steps of;

performing a limited set of functions in the embedded core; and

controlling the non-embedded core using the embedded core.

20. The method of claim 19, wherein the controlling step includes the step of controlling operation of the non-embedded core.

21. The method of claim 20, wherein the controlling step includes the step of controlling the clock rate of the non-embedded core.

22. The method of claim 19, wherein the processor further includes a display controller coupled to the embedded core and non-embedded core, and the method further comprises the step of:

selectively displaying information from the embedded core and the non-embedded core.