Scan cell circuit and scan chain consisting of same for test purpose

• US 20030135803A1
• Filed: 07/16/2002
• Published: 07/17/2003
• Est. Priority Date: 01/17/2002
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Hong, Ted
• Granted Patent: US 6,973,609 B2
• Time in Patent Office: Days
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318541 Scan latches or cell details

Abstract

A scan cell circuit for use in an integrated circuit chip is disclosed. The scan cell circuit includes a multiplexer receiving a first signal, a second signal and a selection signal, and outputting one of the first signal and the second signal in response to the selection signal, and a host circuit electrically connected to the multiplexer, receiving and processing an output of the multiplexer, and proceeding an optional output from a first output end and/or a second output end. When the multiplexer selects the second signal to be outputted in response to a specific state of the selection signal, the first signal output end is fixed at a constant level according to the specific state of the selection signal.

Claims

1. A scan cell circuit for use in an integrated circuit chip, comprising:

a multiplexer receiving a first signal, a second signal and a selection signal, and outputting one of said first signal and said second signal in response to said selection signal; and

a host circuit electrically connected to said multiplexer, receiving and processing an output of said multiplexer, and proceeding an optional output from a first output end and/or a second output end, wherein when said multiplexer selects said second signal to be outputted in response to a specific state of said selection signal, said first signal output end is fixed at a constant level according to said specific state of said selection signal.

2. The scan cell circuit according to claim 1 wherein said first and second signals received by said multiplexer are a test signal and a data signal, respectively, and said multiplexer outputs said test signal when said selection signal is at a high level and outputs said data signal when said selection signal is at a low level.

3. The scan cell circuit according to claim 2 wherein said first and second output ends of said host circuit are a test signal output end and a data signal output end, respectively, and said test signal output end is an output end of a NOR gate, and wherein said NOR gate includes an input end for receiving a leveling signal equivalent to a reverse phase signal of said selection signal to fix an output from said test signal output end at said constant level when said selection signal is at said low level.

4. The scan cell circuit according to claim 2 wherein said first and second output ends of said host circuit are a test signal output end and a data signal output end, respectively, and said test signal output end is an output end of an AND gate, and wherein said AND gate includes an input end for receiving a leveling signal equivalent to said selection signal to further fix an output from said test signal output end at said constant level when said selection signal is at said low level.

5. A digital circuit for use in an integrated circuit chip, performing both testing and data processing operations, and comprising:

a multiplexer receiving a test signal, a data signal and a selection signal, and outputting one of said test signal and said data signal in response to a level state of said selection signal; and

a host circuit electrically connected to said multiplexer, receiving said selection signal and an output of said multiplexer, and performing a level switching operation at a test signal output end and/or a data signal output end in response to said level state of said selection signal, wherein when said multiplexer selects said data signal to be outputted in response to a specific level state of said selection signal, said host circuit has a level at said test signal output end fixed, thereby reducing a power consumption of said integrated circuit chip.

6. The digital circuit according to claim 5 wherein said multiplexer outputs said test signal when said selection signal is at a high level and outputs said data signal when said selection signal is at a low level.

7. The digital circuit according to claim 5 wherein said test signal output end is an output end of a NOR gate, and wherein said NOR gate includes an input end for receiving a reverse phase signal of said selection signal to fix an output of said test signal output end at a low level when said selection signal is at a low level.

8. The digital circuit according to claim 5 wherein said test signal output end is an output end of an AND gate, and wherein said AND gate includes an input end for receiving said selection signal to fix an output of said test signal output end at a low level when said selection signal is at a low level.

9. The digital circuit according to claim 5 wherein said host circuit is a scan cell.

10. The digital circuit according to claim 5 wherein said host circuit is a flip-flop.

11. A level switch digital circuit for use in an integrated circuit chip, comprising:

a multiplexer receiving a first signal, a second signal and a selection signal, and outputting one of said first signal and said second signal in response to a level state of said selection signal; and

a host circuit electrically connected to said multiplexer, receiving and processing an output of said multiplexer, and performing a level switching operation at a first signal output end and/or a second signal output end in response to said level state of said selection signal, wherein when said multiplexer selects said second signal to be outputted in response to a specific state of said selection signal, said host circuit has a level at said first signal output end fixed, thereby reducing a power consumption of said integrated circuit chip.

12. The level switch digital circuit according to claim 11 wherein said first and second signals received by said multiplexer are a test signal and a data signal, respectively, and said multiplexer outputs said test signal when said selection signal is at a high level and outputs said data signal when said selection signal is at a low level.

13. The level switch digital circuit according to claim 12 wherein said first and second output ends of said host circuit are a test signal output end and a data signal output end, respectively, and said test signal output end is an output end of a NOR gate, and wherein said NOR gate includes an input end for receiving a reverse phase signal of said selection signal to fix an output from said test signal output end at said constant level when said selection signal is at said low level.

14. The level switch digital circuit according to claim 12 wherein said first and second output ends of said host circuit are a test signal output end and a data signal output end, respectively, and said test signal output end is an output end of an AND gate, and wherein said AND gate includes an input end for receiving said selection signal to further fix an output from said test signal output end at said constant level when said selection signal is at said low level.

15. The level switch digital circuit according to claim 11 wherein said host circuit is a scan cell.

16. The level switch digital circuit according to claim 11 wherein said host circuit is a flip-flop.

17. A scan chain for use in an integrated circuit chip including a plurality of scan cell circuits connected in series and performing both testing and data processing operations, wherein at least one of said scan cell circuits comprises:

a multiplexer receiving a test signal, a data signal and a selection signal, and outputting one of said test signal and said data signal in response to a level state of said selection signal; and

a host circuit electrically connected to said multiplexer, receiving said selection signal and an output of said multiplexer, and performing a level switching operation at a test signal output end and/or a data signal output end in response to said level state of said selection signal, wherein when said multiplexer selects said data signal to be outputted in response to a specific level state of said selection signal, said host circuit has a level at said test signal output end fixed, thereby reducing a power consumption of said integrated circuit chip.

18. The scan chain according to claim 17 wherein said multiplexer outputs said test signal when said selection signal is at a high level and outputs said data signal when said selection signal is at a low level.

19. The scan chain according to claim 17 wherein said test signal output end is an output end of a NOR gate, and wherein said NOR gate includes an input end for receiving a reverse phase signal of said selection signal to fix an output of said test signal output end at a low level when said selection signal is at a low level.

20. The scan chain according to claim 17 wherein said test signal output end is an output end of an AND gate, and wherein said AND gate includes an input end for receiving said selection signal to fix an output of said test signal output end at a low level when said selection signal is at a low level.