Method of analyzing integrated circuit power distribution in chips containing voltage islands

• US 20030135830A1
• Filed: 01/16/2002
• Published: 07/17/2003
• Est. Priority Date: 01/16/2002
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Proctor, Robert A., Montane, Paul D., Wemple, Ivan L., Kozhaya, Joseph N., Schanzenbach, Erich C., Buffet, Patrick H.
• Granted Patent: US 6,631,502 B2
• Time in Patent Office: Days
• US Class Current: 716/4
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A method of analyzing the power distribution in a chip containing one or more voltage islands, each voltage island having a power distribution network connected to a chip-level power distribution network by one or more voltage translation interface circuits. The method comprising: analyzing the voltage-island power distribution networks independently of the chip-level power distribution network to obtain voltage translation interface circuit currents; using the voltage translation interface circuit currents as input to a model of the chip-level power distribution network to obtain voltage translation interface circuit input voltages; and calculating voltage translation interface circuit output voltages based on the voltage translation interface circuit input voltages, the voltage translation interface circuit currents, and current-voltage characteristics of the voltage translation interface circuits.

Claims

1. A method of analyzing the power distribution in a chip containing one or more voltage islands, each voltage island having a power distribution network connected to a chip-level power distribution network by one or more voltage translation interface circuits comprising:

analyzing said voltage-island power distribution networks independently of said chip-level power distribution network to obtain voltage translation interface circuit currents;

using said voltage translation interface circuit currents as input to a model of said chip-level power distribution network to obtain voltage translation interface circuit input voltages; and

calculating voltage translation interface circuit output voltages based on said voltage translation interface circuit input voltages, said voltage translation interface circuit currents, and current-voltage characteristics of said voltage translation interface circuits.

2. The method of claim 1, wherein said models of said chip-level power distribution network and said voltage-island power distribution network are each selected from the group consisting of passive and linear circuit models.

3. The method of claim 1, wherein said voltage translation interface circuits have linear or nonlinear current-voltage characteristics.

4. The method of claim 1, wherein said model of said chip-level power distribution network and said voltage island power distribution network are each selected from the group consisting of resistive models and resistive-inductive-capacitive models.

5. A method of analyzing power distribution in a chip containing one or more voltage islands, each voltage island having a power distribution network connected to a chip-level power distribution network by one or more voltage translation interface circuits comprising:

(a) creating a chip-level power distribution network model connected to chip-level placed circuits modeled as current sources;

(

b) independently creating a voltage-island power distribution network model connected between voltage translation interface circuit outputs and voltage-island placed circuits modeled as current sources;

(c) obtaining voltage translation interface circuit currents by;

(i) in a first iteration, using the ideal value of an external voltage source as the value of the voltage translation interface circuit output voltages;

(ii) in subsequent iterations using the most recently computed values for the voltage translation interface circuit output voltages; and

{iii) simulating the voltage-island power distribution with its corresponding external voltage sources and the most recently obtained values of the voltage translation interface circuit currents;

(d) exciting said chip-level power distribution with the most recently obtained values of the voltage translation interface circuit currents;

(e) obtaining, through simulation of said chip-level power distribution network, values for the voltage translation interface circuit input voltages and values for the chip-level placed circuit port voltages;

(f) calculating updated values for the voltage translation interface circuit output voltages, based on the most recently obtained values for the voltage translation interface circuit input voltages, the currents through the voltage translation interface circuits, and the current-voltage characteristics of said voltage translation interface circuits; and

(g) comparing the updated values to immediately previous values for the chip-level placed circuit port voltages, voltage translation interface circuit input voltages, and voltage translation circuit output voltages, and, if not converged to within a preset limit, repeating steps (c) through (g).

6. The method of claim 5, wherein said models of said chip-level power distribution network and said voltage-island power distribution network are each selected from the group consisting of passive and linear circuit models.

7. The method of claim 5, wherein said voltage translation interface circuits have linear or nonlinear current-voltage characteristics.

8. The method of claim 5, wherein said model of said chip-level power distribution network and said voltage island power distribution network are each selected from the group consisting of resistive models and resistive-inductive-capacitive models.

9. A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for analyzing power distribution in a chip containing one or more voltage islands, each voltage island having a power distribution network connected to a chip-level power distribution network by one or more voltage translation interface circuits, said method steps comprising:

(a) creating a chip-level power distribution network model connected to chip-level placed circuits modeled as current sources;

(b) independently creating a voltage-island power distribution network model connected between voltage translation interface circuit outputs and voltage-island placed circuits modeled as current sources;

(c) obtaining voltage translation interface circuit currents by;

(i) in a first iteration, using the ideal value of an external voltage source as the value of the voltage translation interface circuit output voltages;

(ii) in subsequent iterations using the most recently computed values for the voltage translation interface circuit output voltages; and

{iii) simulating the voltage-island power distribution with its corresponding external voltage sources and the most recently obtained values of the voltage translation interface circuit currents;

(d) exciting said chip-level power distribution with the most recently obtained values of the voltage translation interface circuit currents;

(e) obtaining, through simulation of said chip-level power distribution network, values for the voltage translation interface circuit input voltages and values for the chip-level placed circuit port voltages;

(f) calculating updated values for the voltage translation interface circuit output voltages, based on the most recently obtained values for the voltage translation interface circuit input voltages, the currents through the voltage translation interface circuits, and the current-voltage characteristics of said voltage translation interface circuits; and

(g) comparing the updated values to immediately previous values for the chip-level placed circuit port voltages, voltage translation interface circuit input voltages, and voltage translation circuit output voltages, and, if not converged to within a preset limit, repeating steps (c) through (g).

11. The program storage device of claim 11, wherein said voltage translation interface circuits have linear or nonlinear current-voltage characteristics.

10. The program storage device of claim 11, wherein said models of said chip-level power distribution network and said voltage-island power distribution network are each selected from the group consisting of passive and linear circuit models.

12. The program storage device of claim 11, wherein said model of said chip-level power distribution network and said voltage island power distribution network are each selected from the group consisting of resistive models and resistive-inductive-capacitive models.

13. A computer system comprising a processor, an address/data bus coupled to said processor, and a computer-readable memory unit coupled to communicate with said processor, said memory unit containing instructions that when executed implement a method for analyzing power distribution in a chip containing one or more voltage islands, each voltage island having a power distribution network connected to a chip-level power distribution network by one or more voltage translation interface circuits, said method comprising the computer implemented steps of:

(a) creating a chip-level power distribution network model connected to chip-level placed circuits modeled as current sources;

(b) independently creating a voltage-island power distribution network model connected between voltage translation interface circuit outputs and voltage-island placed circuits modeled as current sources;

(c) obtaining voltage translation interface circuit currents by;

(i) in a first iteration, using the ideal value of an external voltage source as the value of the voltage translation interface circuit output voltages;

(ii) in subsequent iterations using the most recently computed values for the voltage translation interface circuit output voltages; and

{iii) simulating the voltage-island power distribution with its corresponding external voltage sources and the most recently obtained values of the voltage translation interface circuit currents;

(

d) exciting said chip-level power distribution with the most recently obtained values of the voltage translation interface circuit currents;

(e) obtaining, through simulation of said chip-level power distribution network, values for the voltage translation interface circuit input voltages and values for the chip-level placed circuit port voltages;

(f) calculating updated values for the voltage translation interface circuit output voltages, based on the most recently obtained values for the voltage translation interface circuit input voltages, the currents through the voltage translation interface circuits, and the current-voltage characteristics of said voltage translation interface circuits; and

(g) comparing the updated values to immediately previous values for the chip-level placed circuit port voltages, voltage translation interface circuit input voltages, and voltage translation circuit output voltages, and, if not converged to within a preset limit, repeating steps (c) through (g).

14. The computer system of claim 13, wherein said models of said chip-level power distribution network and said voltage-island power distribution network are each selected from the group consisting of passive and linear circuit models.

15. The computer system of claim 13, wherein said voltage translation interface circuits have linear or nonlinear current-voltage characteristics.

16. The computer system of claim 13, wherein said model of said chip-level power distribution network and said voltage island power distribution network are each selected from the group consisting of resistive models and resistive-inductive-capacitive models.