Half power supply voltage generator and semiconductor memory device using the same

• US 20030137883A1
• Filed: 01/21/2003
• Published: 07/24/2003
• Est. Priority Date: 01/21/2002
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chun, Ki-Chul
• Granted Patent: US 6,781,891 B2
• Time in Patent Office: Days
• US Class Current: 365/189.11
• CPC Class Codes: G05F 1/10 Regulating voltage or current G05F1/02 takes precedence; for electric railways B60M3/02
• CPC Class Codes: G05F 1/465 Internal voltage generators for integrated circuits, e.g. step down generators
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: H01L 21/822 the substrate being a semiconductor, using silicon technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 27/04 the substrate being a semiconductor body

Abstract

The present invention relates to a half power supply voltage generating circuit and a semiconductor memory device having the same. The half power supply voltage generating circuit according to the present invention includes components that allow it to operate regardless of whether the power supply falls below a threshold voltage of included MOS transistors.

Claims

1. A power supply voltage generating circuit for generating an output voltage, comprising:

first active resistor means connected between a supply voltage and a first node, the first active resistor means having a resistance that varies responsive to the output voltage;

first passive resistor means connected in parallel to the first active resistor means;

first voltage regulating means connected between the first node and a second node adapted to regulate a voltage at the first node responsive to a voltage at the second node;

second voltage regulating means connected between the second node and a third node adapted to regulate the voltage at the second node responsive to a voltage at the third node;

second active resistor means connected between the third node and a ground voltage terminal, the second active resistor means having a resistance that varies responsive to the output voltage;

second passive resistor means connected in parallel with the second active resistor means;

a pull-up transistor connected between the supply voltage and the output voltage and adapted to pull up the output voltage responsive to the voltage at the first node; and

a pull-down transistor connected between the ground voltage and the output voltage and adapted to pull down the output voltage responsive to the voltage at the third node.

2. The power supply voltage generating circuit of claim 1 wherein the first active resistor means is a PMOS transistor having a source, a gate, and a drain, the source being connected to the supply voltage, the gate being connected to the output voltage, and the drain being connected to the first node.

3. The power supply voltage generating circuit of claim 2 wherein the source of the PMOS transistor is connected to a substrate on which the PMOS transistor is formed.

4. The power supply voltage generating circuit of claim 1 wherein the first passive resistor means is a resistor.

5. The power supply voltage generating circuit of claim 1 wherein the second active resistor means is an NMOS transistor having a source, a gate, and a drain, the source being connected to the ground voltage, the gate being connected to the third node, and the drain being connected to the output voltage.

6. The power supply voltage generating circuit of claim 1 wherein the second passive resistor means is a resistor.

7. The power supply voltage generating circuit of claim 1 wherein the first voltage regulating means is an NMOS transistor having a source, a gate, and a drain, the source being connected to the first node and the gate and the drain being connected to the third node.

8. The power supply voltage generating circuit of claim 1 wherein the second voltage regulating means is a PMOS transistor having a source, a gate, and a drain, the source being connected to the second node and the gate and the drain being connected to the third node.

9. The power supply voltage generating circuit of claim 1 wherein the pull-up transistor is a NMOS transistor having a source, a gate, and a drain, the source being connected to the output voltage, the gate being connected to the first node, and the drain being connected to the supply voltage.

10. The power supply voltage generating circuit of claim 9 wherein the pull-down transistor is an PMOS transistor having a source, a gate, and a drain, the source being connected to the output voltage, the gate being connected to the third node, and the drain being connected to the ground voltage.

11. The power supply voltage generating circuit of claim 10 wherein the source of the PMOS transistor is connected to a substrate on which the PMOS transistor is formed.

12. Half power supply voltage generating circuit, comprising:

first passive resistor means connected between a supply voltage terminal and a first node;

first active resistor means connected between the supply voltage terminal and the first node, the first active resistor means operating responsive to an output voltage terminal;

first voltage regulating means connected between the first node and a second node and adapted to regulate a voltage at the first node responsive to a voltage at the second node;

second voltage regulating means connected between the second node and a third node and adapted to regulate the voltage at the second node responsive to a voltage at the third node;

second active resistor means connected between the third node and a ground voltage terminal, the second active resistor means operating responsive to an output voltage terminal;

second passive resistor means connected between the third node and the ground voltage terminal;

a pull-up transistor connected between the power supply voltage terminal and the output voltage for pulling up the output voltage responsive to the voltage at the first node; and

a pull-down transistor connected between the third node and the ground voltage terminal for pulling down the output voltage responsive to the voltage at the third node.

13. The half power supply voltage generating circuit of claim 12 wherein the first active resistor means is a PMOS transistor having a source, a gate, and a drain, the source being connected to receive the supply voltage, the gate being connected to receive the output voltage, and the drain being connected to the first node.

14. The half power supply voltage generating circuit of claim 13 wherein the source of the PMOS transistor and a substrate on which the PMOS transistor is formed are commonly connected.

15. The half power supply voltage generating circuit of claim 12 wherein the passive resistor means is a resistor.

16. The half power supply voltage generating circuit of claim 12 wherein the second active resistor means is an NMOS transistor having a source, a gate, and a drain, the source being connected to receive the ground voltage, the gate being connected to receive the output voltage, and the drain being connected to the third node.

17. The half power supply voltage generating circuit of claim 12 wherein the first voltage regulating means is an NMOS transistor having a source, a gate, and a drain, the source and the gate being connected to the third node and the drain being connected to the first node.

18. The half power supply voltage generating circuit of claim 12 wherein the second voltage regulating means is a PMOS transistor having a source, a gate, and a drain, the source being connected to the second node, and the gate and the drain being commonly connected to the third node.

19. The half power supply voltage generating circuit of claim 12 wherein the pull-up transistor is an NMOS transistor having a source, a gate, and a drain, the source being connected to receive the output voltage, the gate being connected to the first node, and the drain being connected to receive the supply voltage.

20. The half power supply voltage generating circuit of claim 19, wherein the pull-down transistor is a PMOS transistor having a source, a gate, and a drain, the source being connected to receive the output voltage, the gate being connected to the third node, and the drain being connected to receive the ground voltage.

21. The half power supply voltage generating circuit of claim 20 wherein the source of the pull-up NMOS transistor and a substrate on which the NMOS transistor is formed are commonly connected.

22. A semiconductor memory device, comprising:

a memory cell array including a plurality of memory cells formed at intersections of a plurality of word lines and a plurality of bit lines;

a pre-charging means adapted to pre-charge the plurality of bit lines with a half power supply voltage; and

a half power supply voltage generating means adapted to generate the half power supply voltage;

wherein the half supply voltage generating means includes;

first active resistor means connected between a supply voltage and a first node, the first active resistor means having a resistance that varies responsive to the output voltage;

first passive resistor means connected in parallel to the first active resistor means;

first voltage regulating means connected between the first node and a second node adapted to regulate a voltage at the first node responsive to a voltage at the second node;

second voltage regulating means connected between the second node and a third node adapted to regulate the voltage at the second node responsive to a voltage at the third node;

second active resistor means connected between the third node and a ground voltage terminal, the second active resistor means having a resistance that varies responsive to the output voltage;

second passive resistor means connected in parallel with the second active resistor means;

a pull-up transistor connected between the supply voltage and the output voltage and adapted to pull up the output voltage responsive to the voltage at the first node; and

a pull-down transistor connected between the ground voltage and the output voltage and adapted to pull down the output voltage responsive to the voltage at the third node.

23. A semiconductor memory device, comprising:

a memory cell array including a plurality of memory cells formed at intersections of a plurality of word lines and a plurality of bit lines;

a pre-charging means adapted to pre-charge the plurality of bit lines with a half power supply voltage; and

a half power supply voltage generating means adapted to generate the half power supply voltage;

wherein the half supply voltage generating means includes;

first passive resistor means connected between a supply voltage terminal and a first node;

first active resistor means connected between the supply voltage terminal and the first node, the first active resistor means operating responsive to an output voltage terminal;

first voltage regulating means connected between the first node and a second node and adapted to regulate a voltage at the first node responsive to a voltage at the second node;

second voltage regulating means connected between the second node and a third node and adapted to regulate the voltage at the second node responsive to a voltage at the third node;

second active resistor means connected between the third node and a ground voltage terminal, the second active resistor means operating responsive to an output voltage terminal;

second passive resistor means connected between the third node and the ground voltage terminal;

a pull-up transistor connected between the power supply voltage terminal and the output voltage for pulling up the output voltage responsive to the voltage at the first node; and

a pull-down transistor connected between the third node and the ground voltage terminal for pulling down the output voltage responsive to the voltage at the third node.