Method and apparatus for managing energy usage of processors while executing protocol state machines

• US 20030137945A1
• Filed: 01/24/2002
• Published: 07/24/2003
• Est. Priority Date: 01/24/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Krishnamurthy, Lakshman, Yavatkar, Rajendra
• Granted Patent: US 7,260,106 B2
• Time in Patent Office: Days
• US Class Current: 370/282
• CPC Class Codes: H04L 12/12 Arrangements for remote connection or disconnection of substations or of equipment thereof
• CPC Class Codes: H04L 47/29 using a combination of thresholds
• CPC Class Codes: H04L 47/30 in combination with information about buffer occupancy at either end or at transit nodes
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/163 In-band adaptation of TCP data exchange; In-band control procedures
• CPC Class Codes: H04L 9/40 Network security protocols
• CPC Class Codes: Y02D 30/00 Reducing energy consumption in communication networks
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A method and apparatus of implementing protocol state machines that conserve energy on energy conscious devices is disclosed. Under this method, most of the energy consuming protocol state machine context invocations or operations are aggregated in time and are scheduled at regular intervals. Such an aggregation leads to many contexts executing concurrently in a burst prior to entering a dormant state. Thus, resource usage can reach a predictable rate pattern of idle and active cycles. With such a pattern, it is possible to take advantage of the energy saving features of processors by downshifting the processor clock speed and use of other resources such as peripherals and buses. The intervals are configured to achieve a tradeoff between timely execution and energy consumption. The aggregation operates across two dimensions, namely, multiple instances of a protocol state machine and multiple layers of protocols in a layered architecture.

Claims

1. A system to manage energy usage of a processor, comprising:

a data communication network;

a transmitter, coupled to the data communication network, to invoke a protocol state machine to send a packet, to wait for an acknowledgment of receipt, and to prepare for a periodic transmission of additional packets;

a receiver, in communication with the transmitter coupled to the data communication network, to receive, process, and verify the packet and send an acknowledgment of receipt;

a buffer, coupled to the protocol state machine, to store the packet; and

a timer, in communication with the transmitter and the receiver, to cause a periodic pattern of packet transmission and reception, wherein the processor is adapted for use in an energy conscious device.

2. The system of claim 1, wherein the data communication network includes at least one of the Internet and an Intranet.

3. The system of claim 1, wherein the transmitter begins in a high power, high clock rate mode.

4. The system of claim 1, wherein the transmitter performs tasks to create packets for transmission.

5. The system of claim 4, wherein the tasks include at least one of dividing data into packets, adding protocol headers, and computing checksums.

6. The system of claim 1, wherein the transmitter enters a low power, low clock rate mode while waiting for an acknowledgment from the receiver.

7. The system of claim 6, wherein the transmitter awakens as at least one of a timer sounds and an incoming packet buffer reaches a low water mark.

8. The system of claim 1, wherein the receiver begins in a low power, low clock rate mode.

9. The system of claim 1, wherein the receiver enters a high power, high clock rate mode when the buffer reaches capacity or a high water mark.

10. The system of claim 1, wherein a frequency setting and a power level of the processor are determined by the transmitted or received packet.

11. The system of claim 10, wherein the periodic pattern in packet transmission and reception are used to manage the frequency setting and power level of the processor.

12. A system to manage energy usage of a processor using at least one protocol state machine comprising a computer readable medium and a computer readable program code stored on the computer readable medium having instructions to:

send a data packet over a data communication network to a receiver protocol state machine that stores the data packet in an application buffer;

wait for an acknowledgment of receipt of the data packet from the receiver protocol state machine; and

arrange for a transmission of additional data packets.

13. The system of claim 12, wherein instructions are provided to a transmitter protocol state machine to send the data packet while in a high power, high clock rate mode.

14. The system of claim 13, wherein instructions are provided to the transmitter protocol state machine to enter an idle low power, low clock rate mode upon completion of data packet transmission.

15. The system of claim 14, wherein instructions are provided to the transmitter protocol state machine to return to a high power, high clock rate mode upon a sounding of a timer.

16. The system of claim 12, wherein an application buffer and a timer cause periodic patterns in data packet transmission, which are used to manage power and frequency of a processor.

17. A system to manage energy usage of a processor using at least one protocol state machine comprising a computer readable medium and a computer readable program code stored on the computer readable medium having instructions to:

receive a data packet from a transmitter protocol state machine over a data communication network;

deposit the data packet in an application buffer;

process and verify the data packet; and

transmit an acknowledgment of receipt of the data packet to the transmitter protocol state machine, wherein the transmitter protocol state machine prepares for transmission of additional data packets.

18. The system of claim 17, wherein instructions are provided to a receiver protocol state machine to obtain delivery of the data packet, to store the data packet in the application buffer, to process the data packet, and to send the acknowledgment of receipt of the data packet.

19. The system of claim 18, wherein instructions are provided to the receiver protocol state machine to enter an idle low power, low clock rate mode upon obtaining delivery of the data packet.

20. The system of claim 19, wherein instructions are provided to the receiver protocol state machine to enter a high power, high clock rate mode when the application buffer reaches a maximum capacity.

21. The system of claim 17, wherein the application buffer and a timer cause periodic patterns in data packet reception, which are used to manage power and frequency of a processor.

22. The system of claim 17, wherein the data communication network includes at least one of the Internet and an Intranet.

23. A method of managing energy usage of a processor using a plurality of transmitter protocol state machines and a plurality of receiver protocol state machines in a multiple layer architecture within a data communication network, comprising:

relaying, from the plurality of transmitter protocol state machines, a data packet to a receiver protocol state machine,

receiving the data packet;

storing the data packet in at least one application buffer;

switching a processor clock mode and a power mode;

processing the buffered data packet;

transmitting the processed data packet; and

delivering the processed data packet to the data communication network.

24. The method of claim 23, wherein the plurality of transmitter protocol state machines commence at an appropriate clock rate for one application among a plurality of applications.

25. The method of claim 24, wherein each application fills one application buffer in a plurality of application buffers.

26. The method of claim 25, wherein the plurality of applications are blocked when at least one application buffer reaches capacity and all buffers contain sufficient data.

27. The method of claim 26, wherein the plurality of receiver protocol state machines are invoked to process the data in the buffers.

28. The method of claim 27, wherein the plurality of transmitter protocol state machines switch the processor clock mode and the power mode to an appropriate mode to process data.

29. The method of claim 23, wherein the plurality of transmitter protocol state machines begin in a high power, high clock rate mode, and the plurality of receiver protocol state machines begin a low power, low clock rate mode.

30. The method of claim 23, wherein the data communication network is at least one of the Internet and an Intranet.