Multigate semiconductor device with vertical channel current and method of fabrication

• US 20030139011A1
• Filed: 09/26/2002
• Published: 07/24/2003
• Est. Priority Date: 08/14/2000
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Cleeves, James M., Subramanian, Vivek
• Granted Patent: US 6,677,204 B2
• Time in Patent Office: Days
• US Class Current: 438/257
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 2211/5611 Multilevel memory cell with more than one control gate
• CPC Class Codes: G11C 2211/5612 Multilevel memory cell with more than one floating gate
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The present invention is a multibit nonvolatile memory and its method of fabrication. According to the present invention a silicon channel body having a first and second channel surface is formed. A charge storage medium is formed adjacent to the first channel surface and a second charge storage medium is formed adjacent to the second channel surface. A first control gate is formed adjacent to the first charge storage medium adjacent to the first channel surface and a second control gate is formed adjacent to the second charge storage medium adjacent to the second surface.

According to the second aspect of the present invention, a transistor is provided that has a source, a channel, a drain, and a plurality of gates where the channel current flows vertically between the source and drain.

According to a third embodiment of the present invention, a memory element is formed using a transistor that has a read current that flows in a direction perpendicular to a substrate in or over which the transistors form. The transistor has a charge storage medium for storing its state. Multiple control gates address the transistor.

Claims

1. A multibit nonvolatile memory comprising:

a silicon channel body having a first and a second channel surface;

a first charge storage medium adjacent to said first channel surface and a second charge storage medium adjacent to said second channel surface;

a first control gate adjacent to said first charge storage medium adjacent to said first channel surface; and

a second control gate adjacent to said second charge storage medium adjacent to said second channel surface.

2. The memory of claim 1 wherein said first and said second control gates are independently controllable.

3. The memory of claim 1 further comprising a third charge storage medium adjacent to a third channel surface of said silicon channel body and a third control gate adjacent to said third charge storage medium.

4. The memory of claim 3 further comprising a fourth charge storage medium adjacent to a fourth surface of said silicon channel body and a fourth control gate adjacent to said fourth charge storage medium.

5. The memory of claim 1 wherein said charge storage medium is an oxide having H+ ion located therein.

6. The memory of claim 1 wherein said charge storage medium is an oxide-nitride-oxide composite film.

7. The memory of claim 1 wherein said charge storage medium comprises nanocrystals.

8. The memory of claim 1 wherein said charge storage medium comprises a continuous film.

9. A multibit nonvolatile pillar memory comprising:

a pillar comprising;

a first source/drain region;

a channel region formed on the first source/drain region;

a second source/drain region formed on the channel region wherein said first source/drain region, said channel region, and said second source/drain region are in alignment and wherein said pillar has a first face and a second face opposite said first face, a third face adjacent to said first face and a fourth face opposite said third face;

a charge storage medium formed adjacent to each of said first, second, third and forth face of said pillar;

a first control gate adjacent to said charge storage medium adjacent to said first face;

a second control gate adjacent to said charge storage medium adjacent to said second face;

a third control gate adjacent to said charge storage medium adjacent to said third face; and

a fourth control gate adjacent to said charge storage medium adjacent to said fourth face.

10. The memory device of claim 9 wherein said charge storage medium is an oxide with H+ ions therein.

11. The memory of claim 9 wherein said charge storage medium is an oxide-nitride-oxide composite film.

12. The memory of claim 9 wherein said charge storage medium comprises nanocrystals.

13. The memory of claim 9 wherein said charge storage medium comprises a continuous film floating gate.

14. The memory of claim 9 wherein the channel region of said first face and the channel region of said third face have a different doping density.

15. The memory of claim 9 wherein the channel region of said first face, the channel region of said second face, the channel region of said third face, and the channel region of said fourth face each have a different doping density.

16. The memory of claim 9 wherein said first source/drain region comprises an N+ doped region formed in a monocrystalline silicon substrate.

17. A method of forming a multibit nonvolatile memory comprising:

forming a plurality of lines comprising silicon films, said plurality of parallel lines having a top surface, a bottom and first and second laterally opposite sidewalls;

forming a first pair of charge storage members adjacent to and in contact with said laterally opposite sidewalls of said plurality of lines;

forming a first pair of control gates adjacent to said charge storage mediums adjacent to said first and second laterally opposite sidewalls;

patterning said first plurality of lines into a plurality of pillars, said pillars having first and second laterally opposite sidewalls;

forming a second pair of charge storage medium adjacent to and in contact with said laterally opposite sidewalls of said pillars; and

forming a second pair of control gates adjacent to and in contact with said second pair of charge storage mediums.

18. A method of forming a multibit nonvolatile memory comprising:

forming a plurality of parallel lines having a top surface and bottom surface wherein the bottom surface is a doped region formed in a monocrystalline silicon substrate;

forming an insulating layer on said monocrystalline silicon substrate between said plurality of lines;

depositing a first charge storage medium between said first plurality of parallel lines;

depositing a first control gate film onto said charge storage medium over and between said first plurality of lines;

etching back said control gate film between said first plurality of lines to a level beneath the top surface of said plurality of lines;

forming an insulating layer on said etched back control gate film between said plurality of lines;

blanketing depositing a polysilicon film over and in contact with said top surface of said plurality of lines and on said insulating oxide between said plurality of lines;

etching said polysilicon film into a second plurality of lines which are perpendicular to said first plurality of lines, and etching said portion of said first plurality of lines not covered by said second plurality of lines to form a plurality of pillars at the intersections of said first and second plurality of lines;

depositing a second charge storage medium between said second plurality of lines and between said pillar; and

depositing a second control gate material on said second charge storage medium between said second plurality of line and between said pillar.

19. A method of fabrication a nonvolatile multibit memory comprising:

forming a first N+ doped region in a P type epitaxial silicon substrate;

growing a P−

type silicon film on said first N+ doped region;

implanting N type impurities into said P type epitaxial film to form a second N+ doped region on said P type epitaxial silicon film;

patterning said first N+ doped region, said P type epitaxial silicon film, and said second N+ doped region into a plurality of parallel lines;

forming a nitride film on the sidewalls of said parallel lines;

oxidizing said substrate to grow an oxide between said plurality of parallel lines;

depositing a charge storage medium over and around and between said plurality of parallel lines;

depositing a first control gate material on said charge storage medium over and around and between said silicon lines;

removing said control gate material between said parallel lines to below the top surface of said second N+ doped region;

blanketing depositing an insulating oxide on said control gate material between said parallel lines and on said charge storage medium on said parallel lines;

removing said insulating oxide and said charge storage medium from the top of said plurality of lines to expose said second N+ doped region;

depositing an N+ polysilicon film over and onto said second N+ doped region and over and onto said insulating oxide on said control gate material between said plurality of lines;

patterning said N+ polysilicon film into a second plurality of parallel lines wherein said second plurality of parallel lines run orthogonal to said first plurality of parallel lines;

continuing the etch of said N+ polysilicon film through said second N+ doped region, said P type epitaxial silicon film, and stopping on said first N+ doped region and thereby forming a plurality of N+/P−

/N+ pillars at the intersections of said first and second plurality of lines;

depositing a second charge storage medium over and around said plurality of pillars;

blanketing depositing a second control gate film over said second charge storage medium; and

etching back said second control gate material.

20. A memory comprising:

a transistor formed on or above a single crystalline substrate, wherein said transistor has a read current that flows in a direction perpendicular to said single crystalline substrate;

a charge storage medium for storing charge adjacent to said transistor; and

a plurality of control gates which address said transistor.

21. A transistor formed on or above a substrate having a plane, the transistor comprising:

a source;

a drain;

a channel wherein the channel current flows perpendicular to the plane of said substrate; and

a plurality of gates.

22. A transistor comprising:

a first source/drain region;

a silicon channel body having a first and a second channel surface formed on said first source/drain region;

a first gate dielectric adjacent to said first channel surface and a second gate dielectric adjacent to said second channel surface;

a second source/drain region on said silicon channel body;

a first gate adjacent to said first charge storage medium adjacent to said first channel surface; and

a second gate adjacent to said second charge storage medium adjacent to said second channel surface.