Dual damascene structure and method of making same

• US 20030139034A1
• Filed: 07/07/2002
• Published: 07/24/2003
• Est. Priority Date: 01/22/2002
• Status: Abandoned Application

• Current Assignee: Yu-Shen Yuang
• Original Assignee: Yu-Shen Yuang
• Inventors: Yuang, Yu-Shen
• Application Number:
  US10/064,364
• Publication Number:
  US 20030139034A1
• Time in Patent Office: Days
• US Class Current: 438/634
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 2221/1031 Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric
• CPC Class Codes: H01L 2221/1036 Dual damascene with different via-level and trench-level dielectrics

Abstract

A dielectric barrier sidewall protected via in combination with a conventional metal barrier is integrated in a dual damascene process. Via reliability, copper filling ability and copper CMP uniformity will be significantly improved according to this invention.

Claims

1. A method of fabricating a copper dual damascene interconnect capable of improving via reliability, comprising the steps of:

providing a substrate having a conductive layer formed thereon;

forming a first dielectric layer over the substrate and the conductive layer;

depositing an etch stop layer on the first dielectric layer;

forming a via opening in the etch stop layer and the first dielectric layer to expose a portion of the conductive layer;

depositing a second dielectric layer over the etch stop layer, sidewalls and bottom of the via opening;

forming a third dielectric layer over the second dielectric layer and the third dielectric layer filling the via opening;

forming a hard mask on the third dielectric layer;

forming a resist layer over the hard mask, the resist layer comprising a line pattern exposing an area of the hard mask overlying the via opening;

etching away the hard mask, the third dielectric layer, the second dielectric layer through the line pattern leaving a portion of the second dielectric layer on sidewalls of the via opening so as to form a via opening protected by a dielectric barrier and a trench overlying the via opening; and

forming a metal barrier on the dielectric barrier, bottom of the via opening and interior surface of the trench.

2. The method according to claim 1 wherein the first and second have a dielectric constant less than 3.2.

3. The method according to claim 1 wherein the dielectric barrier has a thickness of less than 300 angstroms.

4. The method according to claim 1 wherein the second dielectric layer is composed of silicon nitride.

5. The method according to claim 1 wherein the metal barrier is composed of Ta/TaN.

6. A method of fabricating a dual damascene structure capable of improving via reliability, comprising the steps of:

providing a substrate;

forming a conductive layer over the substrate;

forming a cap layer over the conductive layer;

forming a dual damascene opening in a stacked dielectric layer over the substrate to expose a portion of the cap layer above the conductive layer, wherein the dual damascene opening includes a via opening and a trench;

depositing a non-metal barrier layer on the stacked dielectric layer and interior surface of the dual damascene opening;

etching back the non-metal barrier layer to form non-metal barrier spacers on sidewalls of the trench and the via opening and etching away the cap layer to expose the conductive layer through the via opening; and

forming a metal barrier on the non-metal barrier spacers and interior surface of the dual damascene opening not covered by the non-metal barrier spacers.

7. The method according to claim 6 wherein the stacked dielectric layer comprises a first dielectric layer, an etch stop layer on the first dielectric layer, a second dielectric layer atop the etch stop layer, a first hard mask over the second dielectric layer, and a second hard mask over the first hard mask.

8. The method according to claim 7 wherein the first hard mask is composed of silicon nitride and the second hard mask is composed of silicon oxide.

9. The method according to claim 7 wherein the second hard mask is removed during the etch of the cap layer.

10. The method according to claim 6 wherein the non-metal barrier spacer has a thickness of less than 300 angstroms.

11. The method according to claim 10 wherein the non-metal barrier spacer is composed of silicon nitride.

12. The method according to claim 10 wherein the non-metal barrier spacer is formed by plasma enhanced chemical vapor deposition (PECVD).

13. The method according to claim 6 wherein the metal barrier is composed of Ta/TaN.