Speculative read operation

• US 20030140202A1
• Filed: 01/22/2002
• Published: 07/24/2003
• Est. Priority Date: 01/22/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: LaBerge, Paul A.
• Granted Patent: US 6,804,750 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 13/161 with latency improvement

Abstract

A technique for reducing the latency associated with a memory read request. A bypass path is provided to direct the address of a corresponding request to a memory controller. The memory controller initiates a speculative read request to the corresponding address location. In the meantime, the original request is decoded and directed to the targeted area of the system. If the request is a read request, the memory controller will receive the request, and after comparing the request address to the address received via the bypass path, the memory controller will cancel the request since the speculative read has already been issued. If the request is directed elsewhere or is not a read request, the speculative read request is cancelled.

Claims

1. A system for processing a request comprising:

a target component configured to receive a request;

a processor configured to initiate a request, wherein the request comprises an address and a command type corresponding to the target component;

a decoder operably coupled between the target component and the processor and configured to receive the request from the processor and produce a decoded request to the target component based on the address; and

a bypass path configured to receive the request from the processor and produce a bypass request to the target component without implementing the decoder.

2. The system, as set forth in claim 1, wherein the target component comprises a memory system.

3. The system, as set forth in claim 2, wherein the memory system comprises one or more memory devices.

4. The system, as set forth in claim 3, wherein the one or more memory devices comprise synchronous dynamic random access memory (SDRAM) devices.

5. The system, as set forth in claim 3, wherein the memory system comprises a memory controller configured to control access to the one or more memory devices.

6. The system, as set forth in claim 5, wherein the memory controller is operably coupled to each of the decoder and the bypass path.

7. The system, as set forth in claim 6, wherein the memory controller comprises a comparator circuit configured to compare the decoded request received from the decoder and the bypass request received from the bypass path.

8. The system, as set forth in claim 7, wherein the memory controller is configured to cancel the decoded request if the decoded request is the same as the bypass request.

9. The system, as set forth in claim 7, wherein the memory controller is configured to cancel the bypass request if the bypass request is different than the decoded request.

10. The system, as set forth in claim 1, wherein the bypass path comprises one or more repeaters.

11. A system for processing a request comprising:

a first path from a processor controller to a plurality of target locations, wherein the first path comprises a decoder; and

a second path from the processor controller to only one of the plurality of target locations.

12. The system, as set forth in claim 11, comprising a memory controller, and wherein the first path comprises a first branch from the processor controller to the memory controller.

13. The system, as set forth in claim 12, wherein the first path comprises a second branch from the processor controller to an I/O bus.

14. The system, as set forth in claim 12, wherein the second path comprises a third branch from the processor controller to the memory controller.

15. The system, as set forth in claim 12, wherein each of the first path and the second path is configured to deliver requests from the processor controller to the memory controller and wherein the number of clock cycles it takes to deliver the request to the memory controller on the second path is less than the number of clock cycles it takes to deliver the request to the memory controller on the first path.

16. The system, as set forth in claim 12, wherein the memory controller comprises a comparator circuit configured to compare a first request delivered on the first path and a second request delivered on the second path.

17. The system, as set forth in claim 16, wherein the memory controller is configured to cancel the first request if the first request is the same as the second request.

18. The system, as set forth in claim 16, wherein the memory controller is configured to cancel the second request if the second request is different than the first request.

19. The system, as set forth in claim 11, wherein the second path comprises one or more repeaters.

20. The system, as set forth in claim 11, wherein the second path does not comprise a decoder.

21. A method of reducing cycle latency comprising the acts of:

initiating a request wherein the request comprises an address and a command type corresponding to a request destination;

simultaneously directing the request to a decoder via a first path and directing the address to a memory controller via a second path;

receiving the address at the memory controller via the second path at a first time; and

initiating a speculative read request to the address received via the second path.

22. The method of reducing cycle latency, as set forth in claim 21, comprising the acts of:

if the request comprises a memory request, receiving the request at the memory controller via the first path at a second time, wherein the second time is after the first time; and

comparing the request received via the first path with the address received via the second path.

23. The method of reducing cycle latency, as set forth in claim 22, comprising the act of canceling the request received via the first path if the request is a read request comprising the same address as the address received via the second path.

24. The method of reducing cycle latency, as set forth in claim 22, comprising the act of canceling the speculative read request if the request received via the first path is not a read request.

25. The method of reducing cycle latency, as set forth in claim 22, comprising the act of canceling the speculative read request if the address of the request received via the first path is not the same as the address received via the second path.

26. The method of reducing cycle latency, as set forth in claim 21, wherein the act of initiating a request comprises the act of initiating a request by a processor.

27. The method of reducing cycle latency, as set forth in claim 26, wherein the act of simultaneously directing comprises the act of simultaneously directing the request from a processor controller to the decoder and directing the address to the memory controller.

28. The method of reducing cycle latency, as set forth in claim 21, wherein the act of simultaneously directing comprises the act of directing the address and command type to the memory controller via the second path.