Reconfigurable single instruction multiple data array

• US 20030140211A1
• Filed: 05/08/2002
• Published: 07/24/2003
• Est. Priority Date: 01/21/2002
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Kablotsky, Joshua A., Stein, Yosef
• Granted Patent: US 6,865,661 B2
• Time in Patent Office: Days
• US Class Current: 712/15
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses

Abstract

A reconfigurable single instruction multiple data array includes a plurality of processing cells; a serial data bus with at least one line dedicated to each cell; each cell including an identification number for uniquely identifying each cell and its dedicated line and a communication port including at least one parallel to serial transmitter circuit in each cell for broadcasting its cell'"'"'s output data over its dedicated line; at least one serial to parallel receiver circuit in each cell; each cell responsive to the identification number and a common command word to generate a local configuration command designating a pre-selected broadcasting cell and a configuration register associated with each receiver circuit and responsive to the local configuration command to condition its receiver'"'"'s circuit to receive serial input data broadcast from the pre-selected cell'"'"'s dedicated line.

Claims

1. A reconfigurable single instruction multiple data array comprising:

a plurality of processing cells;

a serial data bus with at least one line dedicated to each cell;

each cell including;

an identification number for uniquely identifying each cell and its dedicated line, and

a communication port including;

at least one parallel to serial transmitter circuit in each cell for broadcasting its cell'"'"'s output data over its dedicated line;

at least one serial to parallel receiver circuit in each cell; and

each cell responsive to said identification number and a common command word to generate a local configuration command designating a pre-selected broadcasting cell; and

a configuration register associated with each said receiver circuit and responsive to said local configuration command to condition its receiver circuit to receive serial input data broadcast from said pre-selected cell'"'"'s dedicated line.

2. The reconfigurable single instruction multiple data array of claim 1 in which each said processing cell includes an arithmetic logic unit and a memory.

3. The reconfigurable single instruction multiple data array of claim 1 in which said identification number includes one number which identifies both a said cell and its said dedicated line.

4. The reconfigurable single instruction multiple data array of claim 1 in which said identification number, and the numerical location of the cell'"'"'s dedicated line in a parallel line serial bus are linearly related.

5. The reconfigurable single instruction multiple data array of claim 1 in which said parallel to serial transmitter circuit includes a shift register.

6. The reconfigurable single instruction multiple data array of claim 1 in which said serial to parallel receiver circuit includes a shift register.

7. The reconfigurable single instruction multiple data array of claim 2 in which said arithmetic logic unit includes an arithmetic logic circuit, an adder and a shifter.