Single instruction multiple data array cell

• US 20030140212A1
• Filed: 03/05/2002
• Published: 07/24/2003
• Est. Priority Date: 01/21/2002
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Kablotsky, Joshua A., Stein, Yosef
• Granted Patent: US 6,941,446 B2
• Time in Patent Office: Days
• US Class Current: 712/22
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors

Abstract

A single instruction multiple data (SIMD) array cell for processing a data stream, the array including a plurality of cells, each cell having a memory circuit for storing a predetermined region of the data stream; a location register circuit for representing the size and location of the predetermined region of the data stream; a unique identification number; and an arithmetic logic unit responsive to the identification number and a single command common to all cells in a load mode to compute a unique start position for its cell for receiving the predetermined region of the direct memory access data stream. In an execution mode the command word includes an address field applicable to all cells, a data field and an instruction to be performed by the arithmetic logic unit. The arithmetic logic unit in each cell performs the instruction directly on the local value at that address in its memory with the data in the data field.

Claims

1. A single instruction multiple data (SIMD) array cell for processing a data stream, said array including a plurality of cells, each cell comprising:

a memory circuit for storing a predetermined region of the data stream;

a location register circuit for representing the size and location of the predetermined region of the data stream;

a unique identification number; and

an arithmetic logic unit responsive to said identification number and a single command common to all cells in a load mode to compute the unique start position for its cell for receiving the predetermined region of the direct memory access data stream.

2. The single instruction multiple data array of claim 1 in which said arithmetic logic unit includes an adder circuit.

3. The single instruction multiple data array of claim 2 in which said adder circuit includes a shifter circuit for performing in combination with said adder circuit multiplication and accumulation.

4. The single instruction multiple data array of claim 1 in which said arithmetic logic unit includes an arithmetic logic circuit.

5. The single instruction multiple data array of claim 1 in which the command word in an execution mode includes an address field applicable to all cells and a data field and said arithmetic logic unit operates directly on the value stored at that address in its cell'"'"'s memory with the data in the data field.

6. The single instruction multiple data array of claim 5 in which said command word in said execution mode includes an instruction field for operating said arithmetic logic unit.

7. The single instruction multiple data array of claim 1 in which said arithmetic logic unit includes a multiplexor for presenting inputs from said memory circuit, said command word, said unique identification number, and the output of the arithmetic logic unit.

8. The single instruction multiple data array of claim 1 in which each said cell includes a condition code register and said arithmetic logic unit responds to said unique identification number and said condition code register to control the condition of the cell.

9. The single instruction multiple data array of claim 1 in which said location register circuit stores a start position for the predetermined region to be stored in its memory, the length of the direct memory access data stream to be stored and at least one dimension of the data stream.

10. The single instruction multiple data array of claim 9 in which said location register circuit stores the vertical and horizontal dimension of the data stream.

11. The single instruction multiple data array of claim 1 in which said command word in the execution mode establishes the size and location of predetermined region in the location register circuit.

12. The single instruction multiple data array of claim 1 in which said command word includes an address field for addressing locations in said predetermined region of interest in said memory circuit.

13. The single instruction multiple data array of claim 6 in which said command word in said execution mode includes a data field for operating said arithmetic logic unit.

14. The single instruction multiple data array of claim 5 in which each said cell includes a condition code register and said arithmetic logic unit responds to said unique identification number, said data field, and said condition code register to control the condition of the cell.