Control method, program and computer apparatus for reducing power consumption and heat generation by a CPU during wait

• US 20030140264A1
• Filed: 12/24/2002
• Published: 07/24/2003
• Est. Priority Date: 12/26/2001
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Matsushima, Shinji, Kawano, Seiichi, Yoshiyama, Noritoshi, Komiyama, Hirohide
• Application Number:
  US10/328,808
• Publication Number:
  US 20030140264A1
• Time in Patent Office: Days
• US Class Current: 713/500
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention lowers the performance, and therefore power consumption, of a Central Processing Unit (CPU) to reduce the power consumption when the CPU encounters waiting time due to certain device-related conditions or in the course of execution of a program, thereby reducing power consumption and heat generation in an entire system. Instruction codes to be executed by a CPU and information about a performance for executing the instruction codes are loaded in the CPU and the performance of the CPU is dynamically set at a value determined based on the information about the loaded information about the performance. Thus, the CPU executes the instruction codes at the set performance.

Claims

1. A Central Processing Unit (CPU) control method for controlling the performance of a CPU, comprising the steps of:

loading into said CPU instruction codes to be executed by said CPU and information about the performance for executing said instruction codes;

setting the performance of said CPU at a value determined based on said information about the performance; and

executing said instruction codes by said CPU at said set performance.

2. The CPU control method according to claim 1, further comprising the step of generating correlation information for correlating a memory region in a memory with the information about the performance of said CPU for executing instruction codes loaded in said memory region;

wherein said step of loading said information about the performance into the CPU comprises the steps of;

reading instruction codes to be executed from said memory; and

obtaining information about a performance for executing said instruction codes from said correlation information about said memory region in which said read instruction codes are loaded.

3. The CPU control method according to claim 1, wherein said step of loading into said CPU said information about the performance into the CPU comprises the step of reading a performance specifying instruction specifying the performance of said CPU for executing a predetermined instruction sequence written in a program containing said instruction codes.

4. A CPU control method for controlling the performance of a CPU (Central Processing Unit), comprising the steps of:

setting in a memory a plurality of memory regions correlated with different performances of said CPU; and

,

when instruction codes to be executed is read from said memory, causing said CPU to operate at a performance correlated with said memory region in which said instruction codes are loaded to execute said instruction codes.

5. The CPU control method according to claim 4, wherein said step of setting the memory regions in said memory comprises the step of creating a page table containing information about the performance of the CPU for each page, said page being provided by separating the memory space of said memory.

6. A computer apparatus comprising:

a Central Processing Unit (CPU) for reading and executing instruction codes written in a program; and

clock controller for controlling the operating clock of said CPU,

wherein, when executing given instruction codes, said CPU directs said clock controller to change the operating clock based on information about a performance that is set for said instruction codes.

7. The computer apparatus according to claim 6, further comprising memory in which a plurality of memory regions correlated with different performances of said CPU are set,

wherein said CPU obtains information about said performance to issue a direction to said clock controller based on a memory region out of said memory regions in which instruction codes read from said memory have been loaded.

8. The computer apparatus according to claim 7, further comprising a memory managing module for managing memory space on a page basis and specifying a performance of said CPU on a page basis to correlate said performance with said memory region.

9. The computer apparatus according to claim 6, wherein said CPU reads a performance specifying instruction written in said program that specifies the performance of said CPU for executing a given instruction sequence and issues the direction to said clock controller in accordance with said performance specifying instruction.

10. A computer apparatus comprising a Central Processing Unit (CPU) for reading a program to perform computation and inputting data from and outputting data to an external device;

and

a clock controller for controlling the operating clock of said CPU,

wherein, said CPU direct said clock controller to change the operating clock when performing an I/O-bound process.

11. A computer apparatus comprising:

a Central Processing Unit (CPU) for reading a program to perform computation and inputting data from and outputting data to an external device; and

a clock controller for controlling the operating clock of said CPU;

wherein, said CPU directs said clock controller to change the operating clock when performing an idle loop process to wait for an input.

12. A Central Processing Unit (CPU) capable of controlling a clock generator to change an operating clock, comprising:

an instruction reading module for reading instruction codes from a memory;

an information obtaining module for obtaining information about a performance that is set for said read instruction codes; and

a directing module for issuing a direction to a controller of said clock generator to change the operating clock based on said obtained information about the performance;

wherein said CPU operates in accordance with the operating clock controlled by the direction for changing the operating clock issued to said controller.

13. The CPU according to claim 12, wherein said information obtaining module obtains based on a memory region in which said read instruction codes are loaded the information about said performance that is correlated with said memory region to issue the direction to said controller.

14. The CPU according to claim 13, wherein said information obtaining module obtains the information about the performance of said CPU on a page basis based on memory management information for managing memory space on a page basis.

15. The CPU according to claim 12, wherein, when said instruction reading module reads instruction codes that specifies the performance of said CPU for executing a given instruction sequence, said information obtaining module identifies said instruction codes as the information about said performance.

16. A program for controlling a computer to cause said computer to implement the function of:

setting a plurality of memory regions correlated with different performances of a Central Processing Unit (CPU) in a memory; and

loading instruction codes in a program into one of said memory regions that corresponds to a desired one of said performances of said CPU for executing said instruction codes.

17. A program for controlling a computer to cause said computer to operate as:

processing module for causing a given computation process to be executed; and

an operation control module for causing the performance of said processing module to be changed when said processing module executes an instruction sequence specified in instruction codes in said program.