Functional timing analysis for characterization of virtual component blocks
First Claim
1. A method of analyzing timing in a circuit model, said circuit model including a plurality of inputs and one or more outputs, said plurality of inputs divided into a set of one or more data inputs and a set of one or more control inputs, said method comprising the steps of:
- (a) identifying a set of modes, each of said modes corresponding to a unique combination of control input values for the circuit model;
(b) applying the combination of control input values for one of said modes to the circuit model;
(c) for each data input, calculating a maximum delay for each input/output path not passing through a blocked circuit node for the applied combination of control input values;
(d) recording the maximum delay for each input/output path not passing through a blocked circuit node for the applied combination of control input values; and
(e) repeating steps (b) through (d) for each of the remaining combinations of control inputs within the set of control inputs.
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Abstract
A system and method for performing a timing analysis on virtual component blocks or other circuit models is provided wherein functional information obtained from the circuit'"'"'s control inputs and their useful combinations is used to improve accuracy. The control inputs and data inputs for a circuit block are identified. Each functionally meaningful or useful control input combination is applied to the circuit block, and the topological delay for the data inputs are determined only along the paths that are not blocked by the control inputs. The delays along paths that are blocked are ignored. The analysis is further augmented by determining the topological delay for all paths originating at control inputs, without regard to blocking of paths, so as to reduce the chance for possible underestimation of delays from the data inputs. A final timing model may include the combination of maximum delays along data paths for each combination of control inputs, and maximum delays along paths originating from each of the control inputs. The delay analysis may account for different input slews and load capacitances, and the results may be expressed in tabular or matrix form. A useful technique for condensing time delay information (whether scalar or tabular in form) is also provided, to simplify timing characterization of a virtual component block or circuit model. Delay tables or matrixes that are “close” (i.e., within a specified tolerance) may be combined into a single table or matrix.
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Citations
18 Claims
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1. A method of analyzing timing in a circuit model, said circuit model including a plurality of inputs and one or more outputs, said plurality of inputs divided into a set of one or more data inputs and a set of one or more control inputs, said method comprising the steps of:
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(a) identifying a set of modes, each of said modes corresponding to a unique combination of control input values for the circuit model;
(b) applying the combination of control input values for one of said modes to the circuit model;
(c) for each data input, calculating a maximum delay for each input/output path not passing through a blocked circuit node for the applied combination of control input values;
(d) recording the maximum delay for each input/output path not passing through a blocked circuit node for the applied combination of control input values; and
(e) repeating steps (b) through (d) for each of the remaining combinations of control inputs within the set of control inputs. - View Dependent Claims (2, 3, 4, 5)
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6. A method of analyzing timing in a circuit model, said circuit model including a plurality of inputs, one or more outputs, and a plurality of input/output paths between said plurality of inputs and said one or more outputs, said method comprising the steps of:
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(a) dividing a plurality of inputs for the circuit model into a set of one or more data inputs and a set of one or more control inputs;
(b) identifying a set of modes, each of said modes corresponding to a unique combination of control input values for the circuit model;
(c) applying the combination of control input values for one of said modes to the circuit model;
(d) for each data input, calculating a maximum delay for each input/output path not passing through a blocked circuit node for the applied combination of control input values;
(e) recording the maximum delay for each input/output path not passing through a blocked circuit node for the applied combination of control input values; and
(f) repeating steps (c) through (e) for each of the remaining combinations of control inputs within the set of control inputs. - View Dependent Claims (7, 8)
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9. A computer readable medium having stored therein one or more sequences of instructions for analyzing timing in a circuit model, said circuit model including a plurality of inputs, one or more outputs, and a plurality of input/output paths between said plurality of inputs and said one or more outputs, said one or more sequences of instructions causing one or more processors to perform a plurality of acts, said acts comprising:
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(a) receiving a circuit model;
(b) receiving a set of modes each corresponding to a unique combination of control input values for the circuit model;
(b) applying the combination of control input values for one of said modes to the circuit model;
(c) for each data input, calculating a maximum delay for each input/output path not passing through a blocked circuit node for the applied combination of control input values;
(d) recording, in a data structure, the maximum delay for each input/output path not passing through a blocked circuit node for the applied combination of control input values; and
(e) repeating steps (b) through (d) for each of the remaining combinations of control inputs within the set of control inputs. - View Dependent Claims (10, 11, 12)
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13. A method of merging a set of delay tables, each of said delay tables comprising as elements a plurality of delay values, said method comprising the steps of:
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merging into a new delay table a group of delay tables whose elements fall within a specified tolerance of the elements in similar relative positions of all other delay tables within the group; and
selecting as elements for the new delay table a maximum of all the elements in similar relative positions of all the delay tables in the group. - View Dependent Claims (14)
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16. A method of merging a set of tables into a reduced set of tables, each of said tables comprising a plurality of elements, said method comprising the steps of:
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comparing each element of a given table to a corresponding element in a same relative position in one or more of said tables;
merging said given table with each of said one or more tables when all elements of said given table fall within a specified tolerance of the corresponding element in the same relative position of said one or more of said tables, thereby generating a merged table; and
selecting elements of said merged table from said given table and said one or more of said tables merged with said given table, the selected elements comprising either each element having a maximum value when compared against elements in the same relative position in said given table and said one or more of said tables, or else each having a minimum value when compared against elements in the same relative position in said given table and said one or more of said tables.
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17. A computer readable medium having stored therein one or more sequences of instructions for merging delay tables, each of said delay tables comprising as elements a plurality of delay values, said one or more sequences of instructions causing one or more processors to perform a plurality of acts, said acts comprising:
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receiving said delay tables;
merging into a new delay table a group of delay tables whose elements fall within a specified tolerance of the elements in similar relative positions of all other delay tables within the group; and
selecting as elements for the new delay table a maximum of all the elements in similar relative positions of all the delay tables in the group. - View Dependent Claims (18)
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Specification