Method for manufacturing semiconductor integrated circuit device

• US 20030141557A1
• Filed: 01/31/2003
• Published: 07/31/2003
• Est. Priority Date: 11/15/2001
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Hinoue, Tatsuya, Kamohara, Shiro, Ito, Fumitoshi
• Granted Patent: US 7,067,889 B2
• Time in Patent Office: Days
• US Class Current: 257/391
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518

Abstract

A two-type gate process is suitable for forming a gate insulation film partially formed of a high dielectric film, for example, a titanium oxide film (gate insulation film of the internal circuit) having a relative dielectric constant larger than that of silicon nitride on a substrate, and a silicon nitride film is deposited on the titanium oxide film. The silicon nitride film will prevent oxidation of the titanium oxide film when the surface of the substrate is subjected to thermal oxidation in the next process step. Next, the silicon nitride film and the titanium oxide film on the I/O circuit region are removed, while the silicon nitride film and the titanium oxide film on the internal circuit region remain, and the substrate is subjected to thermal oxidation to form a silicon oxide film as a gate insulation film on the surface of the I/O circuit region.

Claims

1. A semiconductor integrated circuit device comprising:

a first MISFET on a first region of a main surface of a semiconductor substrate; and

a second MISFET on a second region of the main surface of the semiconductor substrate,

wherein a gate insulation film of the first MISFET comprises a first insulation film having a relative dielectric constant higher than that of silicon nitride,

wherein a gate insulation film of the second MISFET comprises a second insulation film consisting of silicon oxide, and

wherein a film thickness, converted to that of a silicon oxide film, of the first insulation film is thinner than a film thickness, converted to that of a silicon oxide film, of the second insulation film.

2. A semiconductor integrated circuit device according to claim 1, wherein the film thickness, converted to that of a silicon oxide film, of the first insulation film is thinner than 3 nm;

and the film thickness, converted to that of a silicon oxide film, of the second insulation film is equal to or thicker than 3 nm.

3. A semiconductor integrated circuit device according to claim 1, wherein the first insulation film consists of an oxide of a 4A group element.

4. A semiconductor integrated circuit device according to claim 1, further comprising a sidewall spacer, comprising (a) a silicon nitride film or (b) a silicon oxide film and a silicon nitride film that covers the sidewall spacer, formed on a sidewall of a gate electrode of the first MISFET.