Power amplifier clipping circuit for minimizing output distortion

• US 20030141928A1
• Filed: 09/11/2002
• Published: 07/31/2003
• Est. Priority Date: 01/26/2002
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jeoung-in
• Granted Patent: US 6,714,074 B2
• Time in Patent Office: Days
• US Class Current: 330/252
• CPC Class Codes: H03F 2203/45398 the AAC comprising a voltage generating circuit as bias circuit for the AAC
• CPC Class Codes: H03F 3/26 Push-pull amplifiers; Phase-splitters therefor duplicated single-ended push-pull arrangements or phase-splitters therefor H03F3/30
• CPC Class Codes: H03F 3/3067 with asymmetrical driving of the end stage
• CPC Class Codes: H03F 3/45089 Non-folded cascode stages
• CPC Class Codes: H03G 11/00 Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general
• CPC Class Codes: H03G 7/06 having semiconductor devices

Abstract

A power amplifier clipping circuit prevents sudden output changes when clipped from excessive input voltage, and includes an input voltage divider, two bias transistors connected to a positive voltage source, a third bias transistor connected to the first bias transistor and a first differential amplifier, a first current source connected to the third bias transistor and a negative voltage source and the first differential amplifier, fourth and fifth bias transistors connected to a negative voltage source and a second differential amplifier, a sixth bias transistor connected to the fourth bias transistor and the second differential amplifier, a second current source connected to the sixth bias transistor and a positive voltage source, a first output voltage controller connected between the negative voltage source and an output with a serial input resistor, and a second output voltage controller connected between the positive voltage source and the output and power amplifier.

Claims

1. A power amplifier clipping circuit comprising:

an input voltage level dividing unit which generates a first dividing voltage and a second dividing voltage that divide an interval to which the level of an input voltage belongs;

a first bias transistor and a second bias transistor which are connected to a positive internal power source voltage, the first and second bias transistors forming a current mirror and providing a bias voltage to a predetermined first differential amplifying unit;

a third bias transistor which is connected to the first bias transistor and provides a bias voltage to the first differential amplifying unit;

a first constant current source which is connected to the third bias transistor and a negative internal power source voltage, and controls the third bias transistor;

the first differential amplifying unit which receives the first dividing voltage and the input voltage, and if the level of the input voltage is between the first dividing voltage and a predetermined first clipping voltage, generates a first output signal, while if the level of the input voltage exceeds the first dividing voltage, generates a second output signal;

a fourth bias transistor and a fifth bias transistor which are connected to a negative internal power source voltage, the fourth and fifth bias transistors forming a current mirror, and providing a bias voltage to a predetermined second differential amplifying unit;

a sixth bias transistor which is connected to the fourth bias transistor and provides a bias voltage to the second differential amplifying unit;

a second constant current source which is connected to the sixth bias transistor and a positive internal power source voltage, and controls the sixth bias transistor;

the second differential amplifying unit which receives the second dividing voltage and the input voltage, and if the level of the input voltage is between a predetermined second clipping voltage and the second dividing voltage, generates a third output signal, while if the level of the input voltage exceeds the second dividing voltage, generates a fourth output signal;

a first output voltage control unit which is connected between the negative internal power source voltage and an output node in which an input resistor that is serially connected to the input voltage is connected to a power amplifier, and in response to the first and second output signals, lowers the level of the input voltage and provides the input voltage to the power amplifier; and

a second output voltage control unit which is connected between the positive internal power source voltage and the output node, and in response to the third and the fourth output signal, raises the level of the input voltage and provides the input voltage to the power amplifier.

2. The power amplifier clipping circuit of claim 1, wherein the input voltage level dividing unit comprises:

a first dividing resistor, an end of which is connected to a positive external power source voltage and the other end of which is connected to a first node generating the first dividing voltage;

a second dividing resistor, an end of which is connected to the first node, and the other end of which is connected to ground;

a third dividing resistor, an end of which is connected to ground, and the other end of which is connected to a second node generating the second dividing voltage; and

a fourth dividing resistor, an end of which is connected to the second node, and the other end of which is connected to a negative external power source voltage.

3. The power amplifier clipping circuit of claim 2, wherein the second dividing resistor and the third dividing resistor have an identical resistance value, and the first dividing resistor and the fourth dividing resistor have an identical resistance value.

4. The power amplifier clipping circuit of claim 2, wherein the gain of the power amplifier is given by the value obtained by dividing the sum of the resistance value of the first dividing resistor and the resistance value of the second dividing resistor by the resistance value of the second dividing resistor.

5. The power amplifier clipping circuit of claim 1, wherein the first differential amplifying unit comprises:

a first drop differential transistor, the collector of which is connected to the collector and base of the second bias, and to the base of which the first dividing voltage is provided;

a second drop differential transistor, the collector of which is connected to the collector and base of the second bias transistor and to the base of which the input voltage is provided;

a third drop differential transistor, the emitter of which is connected to the emitter of the first drop differential transistor, the base of which is connected to the base of the third bias transistor, and the collector of which generates the second output signal;

a fourth differential transistor, the emitter of which is connected to the emitter of the second drop differential transistor, and the base of which is connected to the base of the third bias transistor; and

a first active load unit which is connected between the collectors of the third and fourth drop differential transistors and the negative internal power source voltage, and generates the first output signal.

6. The power amplifier clipping circuit of claim 5, wherein the first active load unit comprises:

a first drop load transistor, the collector of which is connected to the collector of the third drop differential transistor, and the emitter of which is connected to the negative internal power source voltage; and

a second drop load transistor, the collector of which is connected to the collector of the fourth drop differential transistor, the base and collector of which are commonly connected to the base of the first drop load transistor, and the emitter of which is connected to the negative internal power source voltage, wherein the first output signal is output from the bases of the first and second drop load transistors.

7. The power amplifier clipping circuit of claim 5, further comprising:

a plurality of resistance devices between the first and third drop differential transistors, and between the second and fourth drop differential transistors.

8. The power amplifier clipping circuit of claim 1, wherein the first clipping voltage is less than the input voltage of the moment when clipping the output waveform of the power amplifier begins, by 2 n times the threshold voltage of the drop differential transistors, where n denotes the number of drop differential transistors.

9. The power amplifier clipping circuit of claim 8, wherein the input voltage when clipping the output waveform of the power amplifier begins has the same level as the first dividing voltage.

10. The power amplifier clipping circuit of claim 1, wherein the second differential amplifying unit comprises:

a first rise differential transistor, the collector of which is connected to the collector and base of the fifth bias transistor, and to the base of which the second dividing voltage is provided;

a second rise differential transistor, the collector of which is connected to the collector and base of the fifth bias transistor, and to the base of which the input voltage is provided;

a third rise differential transistor, the emitter of which is connected to the emitter of the first rise differential transistor, the base of which is connected to the base of the sixth bias transistor, and the collector of which generates the fourth output signal;

a fourth rise differential transistor, the emitter of which is connected to the emitter of the second rise differential transistor, and the base of which is connected to the base of the sixth bias transistor; and

a second active load unit which is connected between the collectors of the third and fourth rise differential transistors, and the positive internal power source voltage, and generates the third output signal.

11. The power amplifier clipping circuit of claim 10, wherein the second active load unit comprises:

a first rise load transistor, the collector of which is connected to the collector of the third rise differential transistor, and the emitter of which is connected to the positive internal power source voltage; and

a second rise load transistor, the collector of which is connected to the collector of the fourth rise differential transistor, the base and collector of which are commonly connected to the base of the first rise load transistor, and the emitter of which is connected to the positive internal power source voltage, wherein the third output signal is output from the bases of the first and second rise load transistors.

12. The power amplifier clipping circuit of claim 10, further comprising:

a plurality of resistance devices between the first and third rise differential transistors, and between the second and fourth rise differential transistors.

13. The power amplifier clipping circuit of claim 1, wherein the second clipping voltage is greater than the input voltage of the moment when clipping the output waveform of the power amplifier begins, by 2 m times the threshold voltage of the rise differential transistors, where m denotes the number of rise differential transistors.

14. The power amplifier clipping circuit of claim 13, wherein the input voltage of the moment when clipping the output waveform of the power amplifier begins has the same level as the second dividing voltage.

15. The power amplifier clipping circuit of claim 1, wherein the first output voltage control unit comprises:

a first drop control transistor, the emitter of which is connected to the negative internal power source voltage, to the base of which the first output signal is provided, and the collector of which is connected to the output node; and

a second drop control transistor, the emitter of which is connected to the negative internal power source voltage, to the base of which the second output signal is provided, and the collector of which is connected to the output node.

16. The power amplifier clipping circuit of claim 1, wherein the second output voltage control unit comprises:

a first rise control transistor, the emitter of which is connected to the positive internal power source voltage, to the base of which the third output signal is provided, and the collector of which is connected to the output node; and

a second rise control transistor, the emitter of which is connected to the positive internal power source voltage, to the base of which the fourth output signal is provided, and the collector of which is connected to the output node.

17. A method for clipping a power amplifier output, the method comprising:

receiving an input voltage;

generating first and second dividing voltages that divide an interval of the input voltage;

comparing the input voltage with the first dividing voltage and with a predetermined first clipping voltage;

generating a first output signal if the level of the input voltage is between the first dividing voltage and the first clipping voltage;

generating a second output signal if the level of the input voltage exceeds the first dividing voltage;

comparing the input voltage with the second dividing voltage and with a predetermined second clipping voltage;

generating a third output signal if the level of the input voltage is between the second clipping voltage and the second dividing voltage;

generating a fourth output signal if the level of the input voltage exceeds the second dividing voltage;

adjusting downward the level of the input voltage in response to the first and second output signals;

adjusting upward the level of the input voltage in response to the third and fourth output signals; and

providing the adjusted input voltage to the power amplifier.

18. A method as defined in claim 17 wherein at least one of:

the input voltage has the same level as the first dividing voltage at the moment that clipping begins;

the first clipping voltage is a predetermined amount less than the input voltage at the moment that clipping begins; and

the second clipping voltage is a predetermined amount greater than the input voltage at the moment that clipping begins.

19. A clipping circuit for a power amplifier, the clipping circuit comprising:

receiver means for receiving an input voltage;

divider means for generating first and second dividing voltages that divide an interval of the input voltage;

first comparator means for comparing the input voltage with the first dividing voltage and with a predetermined first clipping voltage;

first generator means for generating a first output signal if the level of the input voltage is between the first dividing voltage and the first clipping voltage;

second generator means for generating a second output signal if the level of the input voltage exceeds the first dividing voltage;

second comparator means for comparing the input voltage with the second dividing voltage and with a predetermined second clipping voltage;

third generator means for generating a third output signal if the level of the input voltage is between the second clipping voltage and the second dividing voltage;

fourth generator means for generating a fourth output signal if the level of the input voltage exceeds the second dividing voltage;

first adjuster means for adjusting downward the level of the input voltage in response to the first and second output signals;

second adjuster means for adjusting upward the level of the input voltage in response to the third and fourth output signals; and

provider means for providing the adjusted input voltage to the power amplifier.

20. A clipping circuit as defined in claim 19, further comprising at least one of:

first assignment means for assigning the first dividing voltage substantially equal to the input voltage level at the moment that clipping begins;

second assignment means for assigning the first clipping voltage as a predetermined amount less than the input voltage at the moment that clipping begins; and

third assignment means for assigning the second clipping voltage as a predetermined amount greater than the input voltage at the moment that clipping begins.