High speed differential to single-ended converter

• US 20030141935A1
• Filed: 04/02/2002
• Published: 07/31/2003
• Est. Priority Date: 01/28/2002
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: Integrated Programmable Communications, Inc.
• Inventors: Chen, Yi-Huei, Huang, Po-Chiun
• Granted Patent: US 6,717,474 B2
• Time in Patent Office: Days
• US Class Current: 330/301
• CPC Class Codes: H03F 3/45206 Folded cascode stages

Abstract

A differential to single-ended converter, which is composed of a transconductance amplifier, a current mirror and buffer circuit and a transimpedance stage, is disclosed. A differential voltage signal is provided to the inputs of the transconductance amplifier and converted to a differential current signal. The current mirror and buffer circuit serves as a differential to single-ended current conveyer and isolates the transconductance stage and the following transimpedance stage. Finally, the single-ended current signal is provided to the input of the transimpedance stage and converted to a single-ended current signal.

Claims

1. A differential to single-ended converter comprising:

a transconductance amplifier for receiving a differential voltage signal and converting the differential voltage signal to a differential current signal;

a current mirror and buffer circuit, coupled to the transconductance amplifier, for conveying a differential current signal to a single-ended current signal and isolating the previous transconductance amplifier and the following transimpedance amplifier; and

a transimpedance amplifier, coupled to the current mirror and buffer circuit, for receiving the single-ended current signal and converting the single-ended current signal to a single-ended voltage signal;

wherein the current mirror and buffer circuit provides isolation between the transconductance amplifier and the transimpedance amplifier.

2. The differential to single-ended converter as recited in claim 1, wherein the transconductance amplifier has a degeneration resistor and a transconductance value of the transconductance amplifier is determined by a resistance of the degeneration resistor.

3. The differential to single-ended converter as recited in claim 1, wherein the current mirror and buffer circuit includes a current mirror circuit to achieve current full to single conversion, and a current buffer circuit to achieve isolation between the previous and the following stage.

4. The differential to single-ended converter as recited in claim 1, wherein the transimpedance amplifier has a shunt feedback resistor and a transimpedance of the transimpedance amplifier is determined by a resistance of the shunt feedback resistor.

5. The differential to single-ended converter as recited in claim 1, wherein the transconductance amplifier has a degeneration resistor, the transimpedance amplifier has a shunt feedback resistor, and an overall gain of the differential to single-ended converter is determined by a ratio of resistance values of the degeneration resistor and the shunt feedback resistor.

6. The differential to single-ended converter as recited in claim 1, wherein the transconductance amplifier comprises:

first and second MOS transistors for receiving the differential input signal at their gates and providing the differential input signal at their drains;

a degeneration resistor coupled between sources of the first and second MOS transistors; and

third and fourth MOS transistors having drains coupled to the sources of the first and second transistors, having sources coupled to a first supply node and having gates receiving a bias voltage.

7. The differential to single-ended converter as recited in claim 1, wherein the current mirror and buffer circuit comprises:

fifth and sixth MOS transistors having gates receiving the bias voltage, having sources coupled to a second supply node, and having drains receiving the differential current signal;

seventh and eighth MOS transistors having gates receiving the bias voltage and having sources coupled to the drains of the fifth and sixth MOS transistors, respectively;

a ninth MOS transistor having a drain and a gate coupled to a drain of the seventh MOS transistor and having a source coupled to a first supply node; and

a tenth MOS transistor having a gate coupled to the drain of the seventh MOS transistor, having a source coupled to the first supply node and having a drain coupled to a drain of the eighth MOS transistor and providing the single-ended current signal.

8. The differential to single-ended converter as recited in claim 1, wherein the transimpedance amplifier comprises:

an eleventh MOS transistor having a gate receiving the single-ended current signal and having a source coupled to a second supply node;

a twentieth MOS transistor having a gate coupled to the gate of the eleventh MOS transistor, having a source coupled to a first supply node, and having a drain coupled to a drain of the eleventh MOS transistor for providing the single-ended voltage signal; and

a shunt feedback resistor coupled between the gates and the drains of the eleventh and twentieth MOS transistors.

9. A differential to single-ended converter, comprising:

first and second supply nodes;

first and second MOS transistors having gates receiving a differential input signal;

a degeneration resistor coupled between sources of the first and second MOS transistors;

third and fourth MOS transistors having drains coupled to the sources of the first and second transistors, having sources coupled to the first supply node and having gates receiving a bias voltage;

fifth and sixth MOS transistors having gates receiving the bias voltage, having sources coupled to the second supply node, and having drains coupled to drains of the first and second MOS transistors, respectively;

seventh and eighth MOS transistors having gates receiving the bias voltage and having sources coupled to the drains of the first and second MOS transistors, respectively;

ninth and tenth MOS transistors having drains coupled to drains of the seventh and eighth MOS transistors, respectively, having gates coupled to the drain of the ninth MOS transistor and having sources coupled to the first supply node;

an eleventh MOS transistor having a gate coupled to the drain of the tenth MOS transistor and having a source coupled to the second supply node;

a twentieth MOS transistor having a gate coupled to the drain of the tenth MOS transistor, having a source coupled to the first supply node, and having a drain coupled to a drain of the eleventh MOS transistor; and

a shunt feedback resistor coupled between the gates and the drains of the eleventh and twentieth MOS transistors;

wherein a single-ended output signal is provided by the connected drains of the eleventh and twentieth MOS transistors.

10. The differential to single-ended converter as recited in claim 9, wherein the first and second MOS transistors, the third and fourth MOS transistors, the ninth and tenth MOS transistors and the twentieth MOS transistor are PMOS transistors;

and the fifth and sixth MOS transistors, the seventh and eighth MOS transistors and the eleventh MOS transistor are NMOS transistors.

11. The differential to single-ended converter as recited in claim 9, wherein an overall gain of the differential to single-ended converter is determined by a ratio of resistance values of the degeneration resistor and the shunt feedback resistor.