LCD controller architecture for handling fluctuating bandwidth conditions

• US 20030142058A1
• Filed: 01/31/2002
• Published: 07/31/2003
• Est. Priority Date: 01/31/2002
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Maghielse, William T.
• Application Number:
  US10/062,268
• Publication Number:
  US 20030142058A1
• Time in Patent Office: Days
• US Class Current: 345/98
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

Controlling pixel data typically includes determining whether pixel data from an input FIFO is valid. When a determination is made that the pixel data is invalid, the pixel data is discarded so that invalid pixel data is not written to an output FIFO. A token associated with the pixel data may be asserted when the pixel data is valid. The token associated with the pixel data may be deasserted when the pixel data is invalid. Controlling pixel data also may include writing pixel data to an LCD panel from an output FIFO and stalling a pixel clock when the output FIFO does not contain valid pixel data.

Claims

1. A method of controlling pixel data, the method comprising:

determining whether pixel data from an input FIFO (First-In First-Out) is valid; and

when a determination is made that the pixel data is invalid, discarding the pixel data so that invalid pixel data is not written to an output FIFO.

2. The method of claim 1 further comprising requesting the pixel data from the input FIFO.

3. The method of claim 1 further comprising:

when a determination is made that the pixel data is valid, processing the pixel data so that valid pixel data is written to the output FIFO; and

writing the valid pixel data to the output FIFO.

4. The method of claim 1 further comprising:

asserting a token associated with the pixel data when the pixel data is valid; and

deasserting the taken associated with the pixel data when the pixel data is invalid.

5. The method of claim 1 wherein when the determination is made that the pixel data is invalid, stalling a clock so that invalid pixel data is not written to the output FIFO.

6. The method of claim 1 further comprising when the determination is made that the pixel data is invalid, maintaining a current state in a dithering engine until valid pixel data is available from the input FIFO.

7. The method of claim 1 further comprising when the determination is made that the pixel data is invalid, maintaining a current state in a formatter until valid pixel data is available from the input FIFO.

8. A machine-accessible medium that when accessed, results in a machine performing operations comprising:

determining whether pixel data from an input FIFO (First-In First-Out) is valid; and

when a determination is made that the pixel data is invalid, discarding the pixel data so that invalid pixel data is not written to an output FIFO.

9. The machine-accessible medium of claim 8 wherein:

the machine includes a computer that performs the operations, and

the machine-accessible medium includes a computer-readable medium having stored thereon one or more sequences of instructions for causing the computer to perform the operations.

10. The machine-accessible medium of claim 8 further comprising requesting the pixel data from the input FIFO.

11. The machine-accessible medium of claim 8 further comprising:

when a determination is made that the pixel data is valid, processing the pixel data so that valid pixel data is written to the output FIFO; and

writing the valid pixel data to the output FIFO.

12. The machine-accessible medium of claim 8 further comprising:

asserting a token associated with the pixel data when the pixel data is valid; and

deasserting the token associated with the pixel data when the pixel data is invalid.

13. The machine-accessible medium of claim 8 wherein when the determination is made that the pixel data is invalid, stalling a clock so that invalid pixel data is not written to the output FIFO.

14. The machine-accessible medium of claim 8 further comprising when the determination is made that the pixel data is invalid, maintaining a current state in a dithering engine until valid pixel data is available from the input FIFO.

15. The machine-accessible medium of claim 8 further comprising when the determination is made that the pixel data is invalid, maintaining a current state in a formatter until valid pixel data is available from the input FIFO.

16. A method of controlling pixel data, the method comprising:

writing pixel data to a Liquid Crystal Display (LCD) panel from an output FIFO (First-In First-Out); and

stalling a pixel clock when the output FIFO does not contain valid pixel data.

17. The method of claim 16 further comprising clocking the pixel clock when the output FIFO contains valid pixel data.

18. The method of claim 16 wherein the LCD panel includes a passive matrix LCD panel.

19. The method of claim 16 wherein the LCD panel includes an active matrix LCD panel.

20. A method of controlling pixel data, the method comprising:

writing pixel data to a Liquid Crystal Display (LCD)panel from an output FIFO (First-In First-Out); and

continuously clocking a pixel clock with previously written pixel data that are added to an end of a line on the LCD panel when the output FIFO does not contain valid pixel data until the output FIFO contains valid pixel data.

21. The method of claim 20 wherein the LCD panel includes an active matrix LCD panel.

22. The method of claim 20 wherein the LCD panel includes a passive matrix LCD panel.

23. An apparatus, comprising:

a Direct Memory Access (DMA) engine that is adapted to fetch pixel data;

an input FIFO (First-In First-Out) that is adapted to receive the pixel data from the DMA engine and to indicate whether the pixel data requested from the input FIFO is valid or invalid; and

an output FIFO that is adapted to request the pixel data from the input FIFO, to receive the valid pixel data, and to discard the invalid pixel data.

24. The apparatus of claim 23 further comprising a formatter that is adapted to format the pixel data requested from the input FIFO that is indicated as valid pixel data and to disregard the pixel data that is indicated as invalid pixel data.

25. The apparatus of claim 23 wherein the input FIFO is adapted to assert a token associated with the requested pixel data when the requested pixel data is valid and to deassert the token associated with the requested pixel data when the requested pixel data is invalid.

26. The apparatus of claim 23 further comprising a pixel clock that is adapted to stall when the requested pixel data is invalid.

27. The apparatus of claim 23 further comprising a pixel clock that is adapted to stall when the output FIFO does not contain valid pixel data.

28. The apparatus of claim 23 further comprising a pixel clock that is adapted to continuously clock previously written pixel data to an end of a line on an LCD panel when the output FIFO does not contain valid pixel data.

29. A system, comprising:

a memory that includes pixel data;

a Liquid Crystal Display (LCD) panel; and

a controller that includes;

a Direct Memory Access (DMA) engine that is adapted to fetch the pixel data from the memory;

an input FIFO (First-In First-Out) that is adapted to receive the pixel data from the DMA engine and to indicate whether the pixel data requested from the input FIFO is valid or invalid; and

an output FIFO that is adapted to request the pixel data from the input FIFO, to receive the valid pixel data, to discard the invalid pixel data, and to write the valid pixel data to the LCD panel.

30. The system of claim 29 further comprising a formatter that is adapted to format the pixel data requested from the input FIFO that is indicated as valid pixel data and to disregard the pixel data that is indicated as invalid pixel data.

31. The system of claim 29 wherein the input FIFO is adapted to assert a token associated with the requested pixel data when the requested pixel data is valid and to deassert the token associated with the requested pixel data when the requested pixel data is invalid.

32. The system of claim 29 further comprising a pixel clock that is adapted to stall when the requested pixel data is invalid.

33. The system of claim 29 further comprising a pixel clock that is adapted to stall when the output FIFO does not contain valid pixel data.

34. The system of claim 29 further comprising a pixel clock that is adapted to continuously clock previously written pixel data to an end of a line on the LCD panel when the output FIFO does not contain valid pixel data.