Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor
First Claim
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1. A memory cell, comprising:
- an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor is vertically aligned, and includes a first source/drain region, and a body region;
wherein at least a portion of a lower pillar structure functions as a second source/drain region of the access transistor and wherein at least a portion of the lower pillar structure also functions as a first plate of a trench capacitor;
a single, sub-lithographic gate of the access transistor formed in a trench along only one side of the pillar that is adjacent to the body region wherein only one gate is present between each adjacent pillar; and
a second plate of the trench capacitor.
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Abstract
A circuit and method for a memory cell with a vertical transistor and a trench capacitor. The cell includes an access transistor that is formed in a pillar of a single crystal semiconductor material. The transistor has vertically aligned first and second source/drain regions and a body region. The transistor also includes a gate that is formed along a side of the pillar. A trench capacitor is also included in the cell. A first plate of the trench capacitor is formed integral with the first source/drain region. A second plate is disposed adjacent to the first plate and separated from the first plate by a gate oxide.
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Citations
28 Claims
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1. A memory cell, comprising:
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an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor is vertically aligned, and includes a first source/drain region, and a body region;
wherein at least a portion of a lower pillar structure functions as a second source/drain region of the access transistor and wherein at least a portion of the lower pillar structure also functions as a first plate of a trench capacitor;
a single, sub-lithographic gate of the access transistor formed in a trench along only one side of the pillar that is adjacent to the body region wherein only one gate is present between each adjacent pillar; and
a second plate of the trench capacitor. - View Dependent Claims (2, 3)
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4. A memory device, comprising:
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an array of memory cells, wherein at least one cell includes;
an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor includes a first source/drain region, and a body region;
wherein at least a portion of the pillar functions as a second source/drain region of the access transistor and wherein at least a portion of the pillar also functions as a first plate of a trench capacitor;
a second plate of the trench capacitor;
a number of bit lines that are each selectively coupled to a number of the memory cells at the first source/drain region of the access transistor so as to form columns of memory cells;
a number of word lines, each word line disposed orthogonally to the bit lines with a single word line in each of a number of trenches between rows of the memory cells; and
wherein each single word line addresses gates of access transistors on a first side of a trench, and is isolated from access transistors on a second side of the trench. - View Dependent Claims (5, 6, 7, 8, 9)
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10. A memory array comprising:
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an array of memory cells, each memory cell including an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor is vertically aligned, and includes a first source/drain region, and a body region;
wherein at least a portion of the pillar functions as a second source/drain region of the access transistor and wherein at least a portion the pillar also functions as a first plate of a trench capacitor;
a single, sub-lithographic gate of the access transistor formed in a trench along only one side of the pillar that is adjacent to the body region wherein only one gate is present between each adjacent pillar;
a second plate of the trench capacitor;
a number of word lines interconnecting gates of selected access transistors so as to form a number of rows of memory cells. - View Dependent Claims (11, 12, 13, 14)
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15. A memory cell, comprising:
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an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor is vertically aligned, and includes a first source/drain region, and a body region;
wherein at least a portion of a lower pillar structure functions as a second source/drain region of the access transistor and wherein at least a portion of the lower pillar structure also functions as a first plate of a trench capacitor;
a single, sub-lithographic gate of the access transistor formed in a trench along only one side of the pillar that is adjacent to the body region wherein only one gate is present between each adjacent pillar;
a second plate of the trench capacitor substantially surrounding the first plate portion of the lower pillar structure; and
an ohmic contact that couples the second plate to a layer of semiconductor material. - View Dependent Claims (16, 17)
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18. A memory device, comprising:
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an array of memory cells, wherein at least one cell includes;
an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor is vertically aligned, and includes a first source/drain region, and a body region;
wherein at least a portion of the pillar functions as a second source/drain region of the access transistor and wherein at least a portion the pillar also functions as a first plate of a trench capacitor;
a second plate of the trench capacitor substantially surrounding the first plate portion of the pillar;
an ohmic contact that couples the second plate to a layer of semiconductor material;
a number of bit lines that are each selectively coupled to a number of the memory cells at the first source/drain region of the access transistor so as to form columns of memory cells;
a number of word lines, each word line disposed orthogonally to the bit lines with a single word line in each of a number of trenches between rows of the memory cells; and
wherein each single word line addresses gates of access transistors on a first side of a trench, and is isolated from access transistors on a second side of the trench. - View Dependent Claims (19, 20, 21, 22, 23)
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24. A memory array comprising:
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an array of memory cells, each memory cell including an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor is vertically aligned, and includes a first source/drain region, and a body region;
wherein at least a portion of the pillar functions as a second source/drain region of the access transistor and wherein at least a portion of the pillar also functions as a first plate of a trench capacitor;
a single, sub-lithographic gate of the access transistor formed in a trench along only one side of the pillar that is adjacent to the body region wherein only one gate is present between each adjacent pillar;
a second plate of the trench capacitor substantially surrounding the first plate portion of the pillar;
an ohmic contact that couples the second plate to a layer of semiconductor material;
a number of word lines interconnecting gates of selected access transistors so as to form a number of rows of memory cells. - View Dependent Claims (25, 26)
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27. A memory cell, comprising:
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an access transistor formed in a pillar of single crystal semiconductor material, wherein the transistor is vertically aligned, and includes a first source/drain region, and a body region;
wherein at least a portion of a lower pillar structure functions as a second source/drain region of the access transistor and wherein at least a portion of the lower pillar structure also functions as a first plate of a trench capacitor;
a single, sub-lithographic gate of the access transistor formed in a trench along only one side of the pillar that is adjacent to the body region wherein only one gate is present between each adjacent pillar;
a second polysilicon plate of the trench capacitor substantially surrounding the first plate portion of the lower pillar structure; and
an ohmic contact that couples the second plate to a layer of semiconductor material. - View Dependent Claims (28)
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Specification