Sealing porous structures

• US 20030143839A1
• Filed: 11/22/2002
• Published: 07/31/2003
• Est. Priority Date: 05/15/2000
• Status: Active Grant

• Current Assignee: ASM International NV
• Original Assignee: ASM International NV
• Inventors: Sprey, Hessel, Tuominen, Marko, Raaijmakers, Ivo, Elers, Kai-Erik, Haukka, Suvi, Terhorst, Herbert, Soininen, Pekka T., Hendriks, Menso, Granneman, Ernst
• Granted Patent: US 6,759,325 B2
• Time in Patent Office: Days
• US Class Current: 438/633
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/7681 involving one or more buried masks
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76828 thermal treatment
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76864 Thermal treatment
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 2221/1047 the air gaps being formed by pores in the dielectric
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then the structure is exposed to alternating chemistries to form monolayers of a desired lining material. In exemplary process flows chemical or physical vapor deposition (CVD or PVD) of a sealing layer blocks the pores due to imperfect conformality. An alternating process can also be arranged by selection of pulse separation and/or pulse duration to achieve reduced conformality relative to a self-saturating, self-limiting atomic layer deposition (ALD) process. In still another arrangement, layers with anisotropic pore structures can be sealed by selectively melting upper surfaces. Blocking is followed by a self-limiting, self-saturating atomic layer deposition (ALD) reactions without significantly filling the pores.

Claims

1. A method of fabricating an integrated circuit including a porous insulating layer having a plurality of trenches extending from an upper surface of the insulating layer, the method comprising:

blocking the pores on an exposed surface of the insulating layer, wherein blocking is performed preferentially upon upper surfaces of the insulating layer;

after blocking the pores, forming no more than about one monolayer of a first reactant species in a self-limited and self-saturating reaction; and

reacting a second reactant species with the monolayer.

2. The method of claim 1, wherein blocking comprises melting an upper surface of the insulating layer.

3. The method of claim 2, wherein melting comprises laser annealing.

4. The method of claim 3, wherein melting comprises pulsing laser energy upon the horizontal surfaces of the insulating layer.

5. The method of claim 2, wherein melting comprises directing radiant energy upon horizontal surfaces of the insulating layer.

6. The method of claim 5, wherein radiant energy directly strikes a layer overlying the porous material.

7. The method of claim 1, wherein blocking comprises a deposition process having a reduced conformality compared to an atomic layer deposition selected to have self-saturating and self-limiting surface reactions.

8. The method of claim 7, wherein the deposition process is selected from the group consisting of CVD, PVD and an alternating deposition process that is less conformal than a self-saturating atomic layer deposition (ALD) process.

9. The method of claim 7, wherein the deposition process comprises an alternating deposition process, wherein reactant pulse durations and/or reactant pulse separations are selected to result in conformality between that of pure ALD and pure CVD.

10. A method of depositing a film over a structure having openings therein, comprising an alternating deposition process, whereby a plurality of sequential reactant pulses are separated from one another, the alternating process optimized to achieve a level of conformality between that of atomic layer deposition (ALD) and chemical vapor deposition.

11. A method for controlling conformality of a deposited film on a semiconductor substrate, the method comprising:

providing the substrate with a plurality of openings at a surface thereof;

providing a sequence of at least two different, mutually reactive reactants in temporally separated and alternating reactant pulses;

selecting separations of the reactant pulses and durations of the reactant pulses to control the conformality of the film deposited in the openings in the surface of the semiconductor substrate, wherein the separations and durations are selected to achieve reduced conformality compared to a corresponding atomic layer deposition (ALD) process that is optimized to achieve maximum conformality with minimum cycle length for the substrate topography; and

exposing the semiconductor substrate to the sequence of the reactant pulses with the selected separations and durations to deposit the film.

12. The method of claim 11, wherein a plurality of said openings have widths less than about 1 μ

m.

13. The method of claim 12, wherein a plurality of said openings have widths less than about 0.1 μ

m.

14. A semiconductor fabrication process, comprising:

providing a low k dielectric having an anisotropic pore structure and larger openings therein;

preferentially sealing an upper surface of the low k dielectric layer; and

conducting an atomic layer deposition process to deposit directly over the sealed upper surface.

15. The method of claim 14, wherein preferentially sealing comprises melting a portion of the low k dielectric.

16. The method of claim 15, wherein 1-10 pore depths from the upper surface of the low k dielectric are melted.

17. The method of claim 15, wherein no more than about 3 pore depths from the upper surface of the low k dielectric layer are melted.

18. The method of claim 15, wherein melting comprises directing light energy on the upper surface.

19. The method of claim 18, wherein directing light energy comprises rapid thermal annealing with radiant heat lamps.

20. The method of claim 18, wherein directing light energy comprises pulsing laser energy.

21. The process of claim 14, wherein preferentially sealing comprises depositing a sealing layer with reduced conformality compared to an atomic layer deposition (ALD) process in which self-saturating and self-limiting surface reactions take place within the openings and over the upper surface.

22. The process of claim 21, wherein depositing the sealing layer comprises a chemical vapor deposition process.

23. The process of claim 21, wherein depositing the sealing layer comprises an alternating deposition process wherein reactant pulse durations and/or separations are modified relative to the ALD process.

24. A method for deposition of a film on a semiconductor substrate, the method comprising:

providing the substrate, the substrate having at a surface thereof different regions with different levels of accessibility;

providing a sequence of at least two different, mutually reactive reactants in temporally separated and alternating reactant pulses;

selecting separations of the reactant pulses and/or durations of the reactant pulses to achieve self-saturation and self-limiting atomic layer deposition (ALD) mode deposition on the most accessible regions on the substrate surface and depletion effects in less accessible regions on the substrate surface; and

exposing the semiconductor substrate to the sequence of the reactant pulses with the selected temporal separations and durations to deposit the film.

25. The method of claim 24, wherein the regions comprise top surface reqions.

26. The method of claim 25, wherein the regions further comprise trench regions that are less accessible than the top surface regions.

27. The method of claim 25, wherein the regions comprise pore regions that are less accessible than the top surface regions.

28. The method of claim 24, wherein the separations and durations of the reactant pulses are selected such that significant deposition is prevented in the least accessible regions.

29. The method of claim 24, wherein the separations and durations of the reactant pulses are selected such that in the least accessible regions at the substrate surface the process is at least partially in CVD mode.

30. The method of claim 24, wherein the substrate comprises a porous material, exposed at the surface, and wherein deposition of the film in the porous material is limited to 3 pore depths.