Vehicle electronic control system having fail-safe function

• US 20030144778A1
• Filed: 11/07/2002
• Published: 07/31/2003
• Est. Priority Date: 01/28/2002
• Status: Active Grant

• Current Assignee: Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Original Assignee: DENSO Corporation
• Inventors: Miyano, Hidemasa
• Granted Patent: US 6,892,129 B2
• Time in Patent Office: Days
• US Class Current: 701/29
• CPC Class Codes: F02D 2041/227 Limping Home, i.e. taking specific engine control measures at abnormal conditions
• CPC Class Codes: F02D 41/22 Safety or indicating devices for abnormal conditions in air/fuel ratio feedback systems F02D41/1495, in electric control linkage F02D11/107, in purge control systems F02M25/0809
• CPC Class Codes: F02D 41/266 the computer being backed-up or assisted by another circuit, e.g. analogue

Abstract

A vehicle electronic control system has a control CPU and a monitor CPU. The control CPU performs a fail-safe processing thereby to reduce an engine output torque, when the monitor CPU monitoring the control CPU detects that the control CPU fails to perform throttle control for an engine. When the monitor CPU detects that the control CPU fails to perform the fail-safe processing, it performs a fail-safe processing in place of the control CPU. In this fail-safe processing, the monitor CPU continues to reset the control CPU so that the engine may be forcibly stopped.

Claims

1. A vehicle electronic control system comprising:

a main CPU for performing a fail-safe processing to reduce an output torque of an engine when a failure occurs in an electronic control of a vehicle; and

a sub-CPU provided separately from the main CPU,

wherein the sub-CPU is programmed to determine whether the fail-safe processing is performed properly by the main CPU, and performs a fail-safe processing in place of the main CPU upon determining an abnormality in the fail-safe processing of the main CPU.

2. The vehicle electronic control system as in claim 1, wherein the sub-CPU is programmed to stop the engine, as the fail-safe processing, upon determining the abnormality of the main CPU.

3. The vehicle electronic control system as in claim 2, wherein the sub-CPU is programmed to continue to reset the main CPU upon determining the abnormality in the fail-safe processing of the main CPU.

4. The vehicle electronic control system as in claim 3, wherein the sub-CPU is reset at the same time as the main CPU is reset, and the sub-CPU stores abnormality information indicative of an abnormality of the fail-safe processing of the main CPU in a non-volatile type memory and resets the main CPU based on the abnormality-information.

5. The vehicle electronic control system as in claim 4, wherein the sub-CPU clears the abnormality information stored in the memory upon starting of the engine.

6. The vehicle electronic control system as in claim 4, wherein the sub-CPU clears the abnormality information stored in the memory within a predetermined delay period after turning off an ignition switch.

7. The vehicle electronic control system as claim 1, wherein the sub-CPU outputs a fuel injection stop signal to fuel injectors of the engine upon determining the abnormality in the fail-safe processing of the main CPU.

8. The vehicle electronic control system as in claim 1, wherein the main CPU performs the fail-safe processing to reduce the number of fuel injectors of the engine by which fuel is supplied to the engine, and the sub-CPU outputs a fuel injection stop signal to the fuel injectors which are held inactivated in the fail-safe processing.

9. The vehicle electronic control system as in claim 1, wherein the main CPU performs a throttle control for the engine as well as fuel injection and ignition controls for the engine as the electronic control of the vehicle.

10. The vehicle electronic control system as in claim 9, wherein the sub-CPU is programmed to monitor control operations of the main CPU, and instruct the main CPU to perform the fail-safe processing upon determining the failure in the control operations of the main CPU.