Prediction method and apparatus for delay and skew analysis

• US 20030144825A1
• Filed: 01/28/2002
• Published: 07/31/2003
• Est. Priority Date: 01/28/2002
• Status: Abandoned Application

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Korobkov, Alexander I
• Application Number:
  US10/059,659
• Publication Number:
  US 20030144825A1
• Time in Patent Office: Days
• US Class Current: 703/14
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

The present invention, which may be implemented on a general-purpose digital computer, in certain embodiments includes novel methods and apparatus to provide accurate prediction for skew or delay analysis in complex multi-stage signal paths with mutual couplings between the stages. In some embodiments, single or multiple processors are utilized to implement the present invention.

Claims

1. A method of predicting behavior of a circuit, the method comprising:

dividing the circuit into a plurality of nets, each net including RC elements;

initializing a variable i to 1;

linearly transforming all coupling capacitors that couple a net i to a net i+1;

simulating a net i+1 with an input voltage waveform;

decoupling the net i;

simulating the net i;

storing a result of the act of simulating the net i; and

if a primary output of the circuit is not reached, providing the stored result of simulating the net i to an input of the net i+1 and incrementing i by 1.

2. The method of claim 1 wherein each net excludes any elements selected from a group comprising a transistor and a driver.

3. The method of claim 1 wherein the circuit includes both linear and nonlinear elements.

5. The method of claim 1 further including providing a predefined voltage source to a primary input of the circuit.

6. The method of claim 1 wherein the act of decoupling the net i is accomplished by:

breaking an output connection of the net i gates, and

decoupling all coupling capacitors of the net i+1.

7. The method of claim 1 wherein the result is a waveform.

8. The method of claim 1 wherein simulating a net i+1 is performed while substantially all coupling capacitors coupled to the net i+1, other than between net i and i+1, are grounded with a Miller factor of about 1.

9. The method of claim 1 wherein the decoupling is performed by utilizing a Miller factor.

4. The method 1 wherein the input voltage waveform includes a plurality of waveforms.

10. An article of manufacture comprising:

a machine readable medium that provides instructions that, if executed by a machine, will cause the machine to perform operations including;

dividing a circuit into a plurality of nets, each net including RC elements;

initializing a variable i to 1;

linearly transforming all coupling capacitors that couple a net i to a net i+1;

simulating a net i+1 with an input voltage waveform;

decoupling the net i;

simulating the net i;

storing a result of the act of simulating the net i; and

if a primary output of the circuit is not reached, providing the stored result of simulating the net i to an input of the net i+1 and incrementing i by 1.

11. The article of claim 10 wherein the act of decoupling the net i is accomplished by:

breaking an output connection of the net i gates, and

decoupling all coupling capacitors of the net i+1.

12. The article of claim 10 wherein the circuit includes both linear and nonlinear elements.

13. The article of claim 10 wherein the input voltage waveform includes a plurality of waveforms.

14. An apparatus comprising:

dividing means to divide a circuit into a plurality of nets;

initialization means to initialize a variable i to 1;

transformation means to linearly transforming all coupling capacitors that couple a net i to a net i+1;

first simulation means to simulate a net i+1 with an input voltage waveform;

decoupling means to decouple the net i;

second simulation means for simulating the net i;

storing means to store a result of the second simulation means; and

if a primary output of the circuit is not reached, communication means for providing the stored result of the second simulation means to an input of the net i+1 and incrementation means to increment i by 1.

15. The apparatus of claim 14 wherein each net excludes any elements selected from a group comprising a transistor and a driver.

16. The apparatus of claim 14 wherein the result is a waveform.

17. A circuit simulator for predicting behavior of a circuit, the circuit simulator comprising:

a divider to divide the circuit into a plurality of nets, each net including RC elements;

an initializer to initialize a variable i to 1;

a transformer to linearly transform all coupling capacitors that couple a net i to a net i+1;

a first simulator to simulate a net i+1 with an input voltage waveform;

a decoupler to decouple the net i;

a second simulator to simulate the net i;

a storage to store a result of the second simulator; and

if a primary output of the circuit is not reached, a communication device to provide the stored result of the second simulator to an input of the net i+1 and an incrementor to increment i by 1.

18. The circuit simulator of claim 17 wherein each net excludes any elements selected from a group comprising a transistor and a driver.

19. The circuit simulator of claim 17 wherein the circuit includes both linear and nonlinear elements.

20. The circuit simulator of claim 17 wherein the input voltage waveform includes a plurality of waveforms.

21. The circuit simulator of claim 17 wherein a predefined voltage source is provided to a primary input of the circuit.

22. The circuit simulator of claim 17 wherein the decoupler decouples the net i by:

breaking an output connection of the net i gates, and

decoupling all coupling capacitors of the net i+1 .

23. The circuit simulator of claim 17 wherein the result is a waveform.

24. The circuit simulator of claim 17 wherein the decoupler utilizes a Miller factor.