Method for scan testing and clocking dynamic domino circuits in VLSI systems using level sensitive latches and edge triggered flip floops

• US 20030145264A1
• Filed: 01/30/2002
• Published: 07/31/2003
• Est. Priority Date: 01/30/2002
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Greenhill, David J., Wong, Ban-Pak, Siegel, Joseph R.
• Granted Patent: US 7,000,164 B2
• Time in Patent Office: Days
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G01R 31/318594 Timing aspects clock circuits G01R31/318552

Abstract

A system and method is provided for scan control and observation of a logical circuit that does not halt the operation of the system clock. Thus, all dynamic circuits within the system continue to evaluate and precharge normally. Moreover, the traditional method of placing a multiplexer before the data input of a clocked storage element to perform scan control and observation is no longer required. Consequently, the system and method provide a more efficient manner in which to perform scan control and observation of a logical circuit.

Claims

1. A system for performance of scan control and observation on a circuit of said system, said system having a system clock that runs without interruption to synchronize said scan control and observation of said circuit with logical operation of said circuit, said system comprising:

a clock control circuit synchronized by said system clock to control when said scan control and observation of said circuit occurs, wherein said system clock synchronizes one or more clock signals asserted by said clock control circuit, and

a system controller to control operation of said scan control circuit, wherein said system controller provides said scan control circuit with a plurality of control signals for said performance of said scan control and observation of said circuit.

2. The system of claim 1 wherein said scan control circuit comprises;

a first clock generator circuit to generate a first clock signal synchronous to said system clock, wherein said first clock signal provides said circuit with a clock stimulus to allow said circuit to operate;

a second clock generator circuit to generate a second clock signal synchronous to said system clock, wherein said second clock signal shifts scan data into said circuit for said performance of said scan control and observation;

a third clock generator circuit to generate a third clock signal synchronous to said system clock, wherein said third clock signal shifts said scan data out of said circuit; and

a control circuit to control when said first clock generator circuit, said second clock generator circuit and said third clock generator circuit each generate their respective clock signal.

3. The system of claim 2, wherein said first clock generator circuit comprises,

a latch to generate a time dependent signal synchronous to said system clock;

an output circuit; and

a buffer circuit to drive said output circuit with said time dependant signal from said latch, wherein said output circuit gates said time dependent signal with said system clock to produce said first clock signal.

4. The system of claim 2, wherein said second clock generator circuit comprises,

a latch to generate a time dependent signal synchronous with said system clock;

an output circuit; and

a buffer circuit to drive to said output circuit with said time dependent signal from said latch, wherein said output circuit gates said time dependent signal and said system clock to produce said second clock signal.

5. The system of claim 2, wherein said third clock generator circuit comprises,

a latch to generate a time dependent signal synchronous with said system clock;

an output circuit;

a buffer circuit to drive said output circuit with said time dependent signal from said latch, wherein said output circuit gates said system clock and said time dependant signal to produce a gated signal; and

a output buffer circuit to buffer said gated signal of said output circuit to assert said third clock signal, wherein said output buffer circuit prevents phase overlap of said second clock signal and said third clock signal.

6. The system of claim 2, wherein said control circuit further provides said circuit with an enable signal to control when said circuit evaluates said scan data.

7. The system of claim 1, wherein said circuit comprises a level sensitive logic element.

8. The system of claim 1, wherein said circuit comprises an edge triggered logic element.

9. The system of claim 7, wherein said level sensitive logic element comprises a latch.

10. The system of claim 8, wherein said edge triggered logic element comprises a flip-flop.

11. The system of claim 3, wherein said system controller disables said first clock generator to halt activity in said circuit.

12. The system of claim 3, wherein said output circuit comprises,

one or more NAND gates to gate said time dependant signal and said system clock;

and

one or more buffer elements to buffer each output of said one or more NAND gates.

13. The system of claim 4, wherein said output circuit comprises,

one or more NAND gates to gate said time dependent signal and said system clock;

and

one or more buffer elements to buffer each output of said one or more NAND gates.

14. The system of claim 5, wherein said output circuit comprises,

one or more NOR gates to gate said time dependent signal and said system clock;

and

one or more buffer elements to buffer each output of said one or more NOR gates.

15. The system of claim 1, wherein said system is capable of performing scan control and observation on a dynamic logic circuit that functions based on a rising edge of a clock signal.

16. The system of claim 1, wherein said system is capable of performing scan control and observation on a dynamic logic circuit that functions based on a falling edge of a clock signal.

17. A method for performing scan testing of a logical circuit in an electronic system wherein said logical circuit includes a scan data path and a non-scan data path, said method comprising the steps of:

providing said electronic system with a system clock that runs without interruption;

halting data on said non-scan data path of said logical circuit, to allow scan data to propagate along said scan data path into said logical circuit;

evaluating said scan data to determine an internal state of said logical circuit;

outputting said evaluated scan data from said logical circuit over said scan data path for further evaluation by said electronic system; and

allowing said data on said non-scan data path to propagate to allow said logical circuit to evaluate said non-scan data.

18. The method of claim 17, wherein an enable signal coupled to said logical circuit controls propagation of said data on said non-scan data path of said logical circuit.

19. The method of claim 17, wherein a scan in clock and a scan out clock control propagation of said scan data over said scan data path of said logical circuit.

20. The method of claim 17, wherein said logic circuit comprises a dynamic logic circuit that functions based on a rising edge of a clock signal.

21. The method of claim 17, wherein said logic circuit comprises a dynamic logic circuit that functions based on a falling edge of a clock signal.

22. A method for scan control and observation of an integrated circuit having a scannable circuit, said method comprising the steps of:

generating a system clock for said integrated circuit that runs continually during said scan control and observation of said electronic system; and

controlling operation of said integrated circuit in synchronicity with said system clock to determine an internal state of said scannable circuit of said integrated circuit.

23. The method of claim 22, wherein said step of controlling said integrated circuit comprises the steps of:

generating a first clock signal to control logical operation of said scannable circuit;

generating a second clock signal to allow scan data to propagate into said scannable circuit;

generating a third clock signal to allow said scannable circuit to assert said scan data for said determination of said internal state of said scannable circuit; and

controlling a control signal that allows said scannable circuit to enter a scan state to evaluate said scan data.

24. The method of claim 22, wherein said scannable circuit comprises a level sensitive circuit.

25. The method of claim 24, wherein said level sensitive circuit comprises a latch.

26. The method of claim 22, wherein said scannable circuit comprises an edge triggered circuit.

27. The method of claim 26, wherein said edge triggered circuit comprises a flip-flop.

28. The method of claim 23, further comprising the step of halting said generation of said first clock signal to cease said logical operation in said scannable circuit.

29. The method of claim 23, further comprising the steps of;

halting generation of said second clock signal; and

halting generation of said third clock signal, wherein said halting generation of said second clock signal and said halting generation of said third clock signal prevents said scannable circuit from evaluating scan data without disabling logical operation of said scannable circuit.

30. The method of claim 23, further comprising the step of, controlling an enable signal coupled to said scannable circuit to control when said scannable circuit evaluates scan data and when said scannable circuit evaluates non-scan data.

31. An integrated circuit comprising,

a scannable logic element;

a clock circuit coupled to a system clock that runs continuously to synchronize operation of said clock circuit; and

a control circuit to control operation of said clock circuit, wherein said control circuit provides said clock circuit with control signals to control operation of said scannable logic element.

32. The integrated circuit of claim 31, wherein said clock circuit comprises,

a control circuit;

and

a plurality of clock generation circuits to generate a plurality of clock signals synchronous to said system clock, wherein said control circuit controls when each of said plurality of clock generation circuits generate their respective clock signal.

33. The integrated circuit of claim 32, wherein a control signal of said control circuit coupled to said scannable logic element controls propagation of scan data and non-scan data within said scannable logic element.

34. The integrated circuit of claim 32, wherein said plurality of clock generation circuits comprises,

a first clock generation circuit to generate a first of said plurality of clock signals, wherein said first of said plurality of clock signals allows said scannable logic element to logically operate;

a second clock generation circuit to generate a second of said plurality of clock signals, wherein said second of said plurality of clock signals clocks scan data into said scannable logic element; and

a third clock generation circuit to generate a third of said plurality of clock signals, wherein said third of said plurality of clock signals clocks scan data out of said scannable logic element.

35. The integrated circuit of claim 31, wherein said integrated circuit comprises a very large scale integration (VLSI) circuit.

36. The integrated circuit of claim 35, wherein said very large scale integration circuit comprises a microprocessor.

37. The integrated circuit of claim 31, wherein said scannable logic element comprises a clocked storage element.

38. The integrated circuit of claim 37, wherein said clocked storage element comprises a level sensitive latch.

39. The integrated circuit of claim 37, wherein said clocked storage element comprises an edge triggered flip-flop.