Self-contained embedded test design envoronment and environment setup utility

• US 20030145286A1
• Filed: 12/20/2002
• Published: 07/31/2003
• Est. Priority Date: 01/25/2002
• Status: Active Grant

• Current Assignee: Mentor Graphics Corporation (Siemens AG)
• Original Assignee: Logicvision, Inc. (Siemens AG)
• Inventors: Romain, Luc, Price, Paul, Cote, Jean-Francois, Pajak, Brian John
• Granted Patent: US 6,678,875 B2
• Time in Patent Office: Days
• US Class Current: 716/1
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/318342 by preliminary fault modelling, e.g. analysis, simulation
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

An embedded test, chip design utility is an ease-of-use utility for assisting a circuit designer in quickly implementing a circuit embedded test design flow. Using the utility, a designer transforms a design netlist to include embedded test structures. The utility automatically builds a workspace containing a predetermined repository structure and design environment, generates control files for executing design automation tools that operate within the design flow, and encapsulates the data so as to be self-contained and easily transferable to other design teams.

Claims

1. A circuit design environment setup utility for use in creating a self-contained, design-for-test workspace on a computer readable storage medium for storing design-for test files associated with a circuit block, comprising:

means for generating a circuit block repository on said storage medium, said circuit block repository including a repository for each of predetermined design-for-test flows;

process control file generating means for generating a process control file for predetermined repositories for use in performing predetermined design-for-test operations; and

means for creating soft links to repositories for circuit design files, library files and databases of blocks embedded in said circuit block and storing said soft links in said circuit block repository.

2. A circuit design environment setup utility as defined in claim 1, further including means for generating and storing in each said predetermined repository a process information file associated with each said process control file and describing said operations.

3. A circuit design environment setup utility as defined in claim 1, further including means for generating and storing starter test structure configuration files.

4. A circuit design environment setup utility as defined in claim 1, said means for generating a circuit block repository, including:

means for generating sub-block flow repository;

means for generating a prepare logic flow repository;

means for a generating top-level flow repository; and

means for generating a sign-off repository.

5. A circuit design environment setup utility as defined in claim 4, wherein

said sub-block flow repository being for storing files associated with generating, verifying and assembling said sub-block test structures in said circuit block;

said prepare logic flow repository being for storing files associated with rule analyzing circuit block logic according to design rules, calculating fault coverage, adding test points, creating scan chains and verifying logic test structure operation;

said top-level flow repository being for storing files associated with generating assembling said top-level test structures into said circuit block and verifying all structures inserted into said circuit block; and

said sign-off repository being for verified test structure files.

6. A circuit design environment setup utility as defined in claim 4, said means for generating a sub-block flow repository being further operable to generate:

a sub-block test structure assembly repository for files associated with merging sub-block test structures types into a circuit description of said circuit block; and

a verification repository for files associated with verifying all sub-block test structures types.

7. A circuit design environment setup utility as defined in claim 4, said means for generating sub-block flow repository being further operable to generate a repository for each of one or more types of sub-block test structures.

8. A circuit design environment setup utility as defined in claim 4, said means for generating a top-level flow repository being further operable to generate:

a repository for files associated with said top-level test structures; and

a top level verification repository for files associated with verification of test structures in said circuit block.

9. A circuit design environment setup utility as defined in claim 4, said means for generating a circuit block repository further including means for generating circuit block design environment repositories for design files and libraries and storing therein soft links to said design file and libraries.

10. A circuit design environment setup utility as defined in claim 1, said process control file generating means being operable to generate process control files containing commands for performing predetermined operations, said commands including automation tools commands for generating, verifying and assembling test structures into said circuit block.

11. A circuit design environment setup utility as defined in claim 10, said commands being arranged into targets, each target corresponding to a phase of a corresponding design flow and comprising a predetermined sequence of automation tool commands for performing said operations, each said target being executable independently of other targets or executable in a sequence.

12. A circuit design environment setup utility as defined in claim 1, said soft links pointing to associated library storage locations and files and said commands referring to library storage locations using a relative path contained within said design environment repositories.

13. A circuit design environment setup utility as defined in claim 1, further including means for generating a workspace configuration file.

14. A circuit design environment setup utility as defined in claim 13, said means for generating a workspace configuration file including means for inserting into said configuration file:

a global options section defining global conditions in effect throughout implementation of an embedded test design flow of said circuit block;

a design environment options section defining design environment repositories to be included in said workspace, environment parameters and relative links indicating a path from said design environment repositories to a location of design data;

a design flow options section specifying a design module target type indicative of test structure types to be integrated into said circuit block; and

a test structure requirements section identifying test structures to be incorporated into said circuit block.

15. A circuit design environment setup utility as defined in claim 14, each said test structure requirements section including test structure design parameters corresponding to a test structure type and a default value for each said parameter.

16. A circuit design environment setup utility as defined in claim 14, further including means for inserting descriptive comments into said workspace configuration file.

17. A circuit design environment setup utility as defined in claim 14, said means for generating a workspace configuration file being responsive to a target type specified in a utility command line option for generating a workspace corresponding to a predetermined block design-for-test flow.

18. A circuit design environment setup utility as defined in claim 17, said target type including a top module design flow for use in specifying top module test structures to be added to a top module of said circuit block, said top module test structures including one or more of a test access port, boundary scan cells, and a top-level logic test controller.

19. A circuit design environment setup utility as defined in claim 17, said target type including a sub-block design flow for specifying sub-block test structures for sub-blocks in a circuit block.

20. A circuit design environment setup utility as defined in claim 17, said target type including a legacy core design flow for specifying test access and isolation for a legacy core circuit block.

21. A circuit design environment setup utility as defined in claim 17, said target type including an embedded logic core design flow for integrating logic test circuitry into a core and encapsulating said core in a collar so as render said core to be self-testing and reusable in a hierarchical manner.

22. A circuit design environment setup utility as defined in claim 14, said design environment options section defining a name and location of each of predetermined libraries, files, and repositories and workspaces of blocks embedded in said circuit block.

23. A circuit design environment setup utility as defined in claim 1, further including means for parsing a workspace configuration file.

24. A circuit design environment setup utility as defined in any one of the preceding claims, each said means being a computer executable program code segment.

25. A self-contained, circuit design framework for use in a computer readable storage medium for storing files associated with designing a circuit block according to a design flow having a plurality of phases and using design automation tools for generating said test files, said framework comprising:

a circuit block repository having;

design environment repositories containing soft links to design libraries and files so that all scripts referring to said design libraries and files use a relative path to said soft links contained within said design environment repositories;

a design flow repository for each phase of said plurality of design flow phases;

a process control file in said circuit block repository and each said design flow repository for use in performing predetermined operations; and

a design flow configuration file in each said design flow repository for use in specifying design flow options and parameter values.

26. A self-contained embedded test design framework as defined in claim 25, further including a process information file corresponding to each process control file and describing said operations.

27. A self-contained embedded test design framework as defined in claim 25, wherein the process control file in said circuit block repository is a parent process control file for executing all of said design flow phases.

28. A self-contained embedded test design framework as defined in claim 25, each said process control file containing one or more selectable targets for executing a corresponding sequence of steps of said corresponding design flow phase.

29. A self-contained embedded test design framework as defined in claim 25, said design flow repository being a design-for-test repository including:

a sub-block flow repository;

a prepare logic flow repository;

a top-level flow repository; and

a sign-off flow repository.

30. A self-contained embedded test design framework as defined in claim 29, said sub-block flow repository being for storing files associated with generating and verifying sub-block test structures and assembling said sub-block test structures in said circuit block;

said prepare logic flow repository being for storing files used for rule analyzing design files, calculating fault coverage, adding test points and/or scan chains and verification of logic test structure operation;

said top-level flow repository being for files associated with generating and assembling top-level test structures into said circuit block and verifying all test structures in said circuit block; and

said sign-off flow repository being for verified test structure files.

31. A self-contained embedded test design framework as defined in claim 29, said sub-block flow repositories including:

a repository for each type of sub-block test structure, each said sub-block test structure type repository including;

a sub-block test structure generation flow repository for use in generating said sub-block test structure; and

a sub-block test structure output repository for storing generated sub-block test structure files and for verifying said sub-block test structure prior to assembly thereof into said circuit block;

a sub-block test structure assembly flow repository for merging sub-block test structures into said circuit block; and

a verification flow repository for verification of test structures integrated into said circuit block.

32. A self-contained embedded test design framework as defined in claim 29, said top-level flow repository including:

a top-level test structure generation flow repository for files associated with generating top-level test structures and assembling said top-level test structures into said circuit block; and

a top-level verification flow repository for files associated with verification of a test ready circuit block.

33. A self-contained embedded test design framework as defined in claim 29, each said design flow repository further having a process control file for use in performing a test structure design flow within said repository.

34. A self-contained embedded test design framework as defined in claim 33, said process control files including:

a parent process control file stored in said circuit block repository; and

child process control files stored in each said flow repository;

said parent process control file being operable to execute all child process control files in a predetermined sequence.

35. A self-contained embedded test design framework as defined in claim 25, each said flow repository further including a process information file describing procedures for performing a test structure design flow within said repository.

36. A self-contained embedded test design framework as defined in claim 25, each said design flow repository further including a starter flow configuration file for use in configuring a corresponding test structure.

37. A self-contained embedded test design framework as defined in claim 29, said sign-off flow repository containing a concatenated netlist for a complete circuit design, a final set of test vectors for logic testing of said circuit block, test patterns for all the embedded test structures in said circuit, timing analysis scripts for performing analysis of the embedded test structures in the circuit, and test benches for performing simulation of all embedded test structures through a top level of said circuit block.

38. A self-contained embedded test design framework as defined in claim 25, further including a repository for a hand-off database including a circuit block handoff repository for selected files from said flow repositories.

39. A self-contained embedded test design framework as defined in claim 38, said selected files including:

descriptions of all test steps that are to be performed during manufacturing test;

descriptions of test-collared versions of said circuit sub-blocks and of connections of collared sub-block test ports;

descriptions of external scan chains in said test-collared test sub-block;

descriptions of the periphery logic of said test-collared blocks added to sub-blocks;

descriptions of all embedded test capabilities of said circuit block.

40. A self-contained embedded test design framework as defined in claim 39, said selected files further including descriptions of any specified physical constraints to enable grouping and port polarity 41. A self-contained embedded test design framework as defined in claim 39, said selected files further including descriptions contained in a boundary scan description language file generated during generation and integration of said top-level test structures into said circuit block.