Idle-pattern output control circuit used in a Gigabit Ethernet-passive optical network

• US 20030147654A1
• Filed: 01/30/2003
• Published: 08/07/2003
• Est. Priority Date: 02/01/2002
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Tae-Sung, Sung, Whan-Jin, Won, Shin-Hee, Lee, Min-Hyo
• Granted Patent: US 7,274,874 B2
• Time in Patent Office: Days
• US Class Current: 398/168
• CPC Class Codes: H04L 2007/045 Fill bit or bits, idle words
• CPC Class Codes: H04L 7/06 the synchronisation signals differing from the information signals in amplitude, polarity or frequency or length
• CPC Class Codes: H04Q 11/0062 Network aspects
• CPC Class Codes: H04Q 11/0066 Provisions for optical burst or packet networks
• CPC Class Codes: H04Q 11/0067 Provisions for optical access or distribution networks, e.g. Gigabit Ethernet Passive Optical Network (GE-PON), ATM-based Passive Optical Network (A-PON), PON-Ring
• CPC Class Codes: H04Q 2011/0094 Star

Abstract

An idle pattern output-control circuit used in a point-to-multipoint communication based Gigabit Ethernet-passive optical network (GE-PON) is provided to prevent data loss caused by an idle pattern in a Gigabit-Ethernet controller. In a GE-PON having an optical-line terminal (OLT), a plurality of optical-network units (ONUs) connected to each other via an optical-distribution network (ODN), a media-access controller (MAC), and a physical-coding sublayer (PCS), in which the PCS transmits idle-pattern data to a serializer/deserializer (SERDES) when there is no data to be transmitted to the OLT, an idle-pattern output-control circuit comprising a data converter for converting an idle-pattern data generated from the PCS into a low-level optical signal for subsequent transmission to the OLT, and a switching circuit for selecting data generated from the PCS for subsequent transmission to the SERDES when there is data to be transmitted and for selecting data converted by the data converter for subsequent transmission to the SERDES when there is no data to be transmitted.

Claims

1. An idle-pattern output-control circuit used in a Gigabit Ethernet-passive optical network having at least one optical-line terminal (OLT) and a plurality of optical-network units (ONUs) connected as a Gigabit Ethernet to each other via an optical-distribution network (ODN), said ONU including a media-access controller (MAC) and a physical-coding sublayer (PCS), said PCS transmitting idle-pattern data to a serializer/deserializer (SERDES) when there is no data to be transmitted to said OLT, said idle-pattern output-control circuit comprising:

a data converter for converting said idle-pattern data into a low-level optical signal for transmission to said OLT; and

a switching circuit for selecting data generated from said PCS for transmission to said SERDES if there is data to be transmitted, and for selecting data converted by said data converter for transmission to said SERDES if there is no data to be transmitted.

2. The idle-pattern output-control circuit according to claim 1, wherein said data converter comprises:

an inverter for inverting said idle-pattern data;

a buffer for buffering said idle-pattern data to correspond to a time delay of data passing through said inverter; and

,

an AND gate for combining outputs of said inverter and said buffer.

3. The idle-pattern output-control circuit according to claim 1, wherein the presence and absence of data to be transmitted from said switching circuit is determined by a transmission-enable signal generated from said MAC.

4. The idle-pattern output-control circuit according to claim 3, wherein said idle-pattern data is alternatively repeated data of logic “

1” and

“

0”

, and wherein said data converted by said data converter is consecutively repeated data of logic “

0”

.

5. The idle-pattern output-control circuit according to claim 1, wherein said switching circuit comprises a 1:

2 switch and a 2;

1 switch.