Wafer interposer assembly and system for building same

• US 20030148108A1
• Filed: 02/24/2003
• Published: 08/07/2003
• Est. Priority Date: 12/15/2000
• Status: Active Grant

• Current Assignee: Mind Fusion, LLC (Ascend Innovation Management, LLC)
• Original Assignee: Micro-ASI, Inc. (Calmare Therapeutics Incorporated)
• Inventors: Pierce, John L.
• Granted Patent: US 6,933,617 B2
• Time in Patent Office: Days
• US Class Current: 428/413
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01075 Rhenium [Re]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: Y10T 428/31511 Of epoxy ether

Abstract

A wafer interposer assembly and a system for building the same are disclosed. The wafer interposer assembly includes a semiconductor wafer (10) having a die (11) and a redistribution layer pad (13) electrically connected to the die (11). An epoxy layer (20) is deposited on the surface of the redistribution layer pad (13) and the die (11). An interposer pad (50) is positioned in an opening (40) in the epoxy layer (20) in electrical contact with the redistribution layer pad (13).

Claims

1. A wafer interposer assembly comprising:

a semiconductor wafer having a die;

a redistribution layer (RDL) pad electrically connected to the die;

an epoxy layer deposited on the surface of the redistribution layer pad and the die, the epoxy layer having an opening therethrough about the redistribution layer pad; and

an interposer pad positioned in the opening in electrical contact with the redistribution layer pad.

2. The wafer interposer assembly as recited in claim 1, wherein the semiconductor wafer includes a plurality of die.

3. The wafer interposer assembly as recited in claim 1, wherein the redistribution layer pad comprises a material reflective to laser frequencies.

4. The wafer interposer assembly as recited in claim 1, wherein the redistribution layer pad comprises a material compatible with solder.

5. The wafer interposer assembly as recited in claim 1, wherein the redistribution layer pad comprises a material compatible with conductive polymer.

6. The wafer interposer assembly as recited in claim 1, wherein the epoxy layer is disposed on the surface by a deposition process selected from the group consisting of spraying, rolling and vapor deposition.

7. The wafer interposer assembly as recited in claim 1, wherein the epoxy layer comprises a nonconductive material having a coefficient of thermal expansion similar to the wafer.

8. The wafer interposer assembly as recited in claim 1, wherein the height of the epoxy layer is at least the length of the redistribution layer pad.

9. The wafer interposer assembly as recited in claim 1, wherein the epoxy layer is cured.

10. The wafer interposer assembly as recited in claim 1, wherein the epoxy layer is cured by a processes selected from the group consisting of heat processes and chemical processes.

11. The wafer interposer assembly as recited in claim 1, wherein the epoxy layer is trimmed to achieve a flat surface and controlled height.

12. The wafer interposer assembly as recited in claim 1, wherein the epoxy layer is trimmed by a laser process to achieve a flat surface and controlled height.

13. The wafer interposer assembly as recited in claim 1, wherein the interposer pad comprises a conductive material.

14. The wafer interposer assembly as recited in claim 1, wherein the opening is formed by a laser process.

15. The wafer interposer assembly as recited in claim 1, further comprising an epoxy coat disposed on a backside of the wafer.

16. A wafer interposer assembly comprising:

a semiconductor wafer having a plurality of die;

a plurality of redistribution layer pads electrically connected to each die, the redistribution layer pads including a material reflective to laser frequencies;

an epoxy layer deposited on the surface of the redistribution layer pads and the dies, the epoxy layer having a plurality of openings therethrough corresponding to the redistribution layer pads, the epoxy layer having a flat surface that is trimmed to a height of at least the length of the redistribution layer pads; and

a plurality of interposer pads positioned in the openings in electrical contact with the redistribution layer pads.

17. The wafer interposer assembly as recited in claim 16, wherein the epoxy layer is trimmed by a laser process to achieve a flat surface and controlled height.

18. The wafer interposer assembly as recited in claim 16, wherein the openings are formed by a laser process.

19. A system for building a wafer interposer assembly, comprising:

a depositor that deposits an epoxy layer onto the surface of a semiconductor wafer having a plurality of die and a plurality of redistribution layer pads electrically connected to each die;

a laser that operates relative to the semiconductor wafer to trim the epoxy layer to a flat surface and controlled height and to bore a plurality of openings in alignment with the redistribution layer pads through the epoxy layer; and

a screener that screens an interposer pad into the openings and into electrical contact with the redistribution layer pads.

20. The system as recited in claim 19, wherein the depositor is selected from the group consisting of spraying depositors, rolling depositors and vapor depositors.

21. The system as recited in claim 19, wherein the laser operates under the control of a controller.

22. The system as recited in claim 21, wherein the controller comprises a computer-numerical-control machine that maneuvers and operates the laser in three dimensions.

23. The system as recited in claim 19, wherein the controlled height of the epoxy layer is at least the length of the redistribution layer pad.

24. The system as recited in claim 19, further comprising a curing means for curing the epoxy layer.

25. The system as recited in claim 24, wherein the curing means employs a heat process.

26. The system as recited in claim 24, wherein the curing means employs a chemical process.

27. The system as recited in claim 19, wherein the screener screens a conductive material into the openings to form the interposer pads.

28. The system as recited in claim 19, further comprising an alignment mark position on the semiconductor wafer to provide orientation to the laser.

29. The system as recited. in claim 19, wherein the depositor deposits an epoxy coat on the backside of the semiconductor wafer.

30. The system as recited in 29, wherein the laser adjusts the height of the epoxy coat.