CMOS imager with a self-aligned buried contact
First Claim
1. An imaging device comprising:
- a substrate;
a photosensitive area within said substrate for accumulating photo-generated charge in said area;
a floating diffusion region in said substrate for receiving charge from said photosensitive area;
a readout circuit comprising at least an output transistor formed in said substrate; and
, a self-aligned buried contact for interconnecting said floating diffusion region with said output transistor.
2 Assignments
0 Petitions
Accused Products
Abstract
An imaging device formed as a CMOS semiconductor integrated circuit includes a buried contact line between the floating diffusion region and the gate of a source follower output transistor. The self-aligned buried contact in the CMOS imager decreases leakage from the diffusion region into the substrate which may occur with other techniques for interconnecting the diffusion region with the source follower transistor gate. Additionally, the self-aligned buried contact is optimally formed between the floating diffusion region and the source follower transistor gate which allows the source follower transistor to be placed closer to the floating diffusion region, thereby allowing a greater photo detection region in the same sized imager circuit.
39 Citations
139 Claims
-
1. An imaging device comprising:
-
a substrate;
a photosensitive area within said substrate for accumulating photo-generated charge in said area;
a floating diffusion region in said substrate for receiving charge from said photosensitive area;
a readout circuit comprising at least an output transistor formed in said substrate; and
,a self-aligned buried contact for interconnecting said floating diffusion region with said output transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
-
-
20. An imaging device comprising:
-
a substrate having a photosensitive area therein for accumulating photo-generated charge in said area;
a region in said substrate for receiving charge from said photosensitive area;
a device for controlling said charge, said device including a conductive layer, an insulating layer over said conductive layer and an insulating spacer adjacent said conductive layer; and
,a buried contact adjacent said insulating spacer for interconnecting said region with said device. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28)
-
-
29. An imaging device comprising
a semiconductor integrated circuit substrate; -
a photosensitive device formed on said substrate for accumulating photo-generated charge in an underlying region of said substrate;
a floating diffusion region in said substrate for receiving said photo-generated charge;
a readout circuit comprising at least an output transistor formed in said substrate; and
said floating diffusion region being connected to said output by a self-aligned buried contact via interconnectors. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52)
-
-
53. A processing system comprising:
-
(i) a processor; and
(ii) a CMOS imaging device coupled to said processor and including;
a substrate;
a photosensitive area within said substrate for accumulating photo-generated charge in said area;
a floating diffusion region in said substrate for receiving charge from said photosensitive area;
a readout circuit comprising at least an output transistor formed in said substrate; and
,a self-aligned buried contact for interconnecting said floating diffusion region with said output transistor. - View Dependent Claims (54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71)
-
-
72. An imaging device comprising:
-
a substrate;
a photosensitive area within said substrate for accumulating photo-generated charge in said area;
a readout circuit comprising at least an output transistor formed in said substrate; and
,a self-aligned buried contact formed over a doped region in said substrate and between two structures on said substrate for electrically connecting said imaging device, wherein said structures are selected from a transistor gate and an isolation region. - View Dependent Claims (73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92)
-
-
93. A processing system comprising:
-
(i) a processor; and
(ii) a CMOS imaging device coupled to said processor and including;
a substrate;
a photosensitive area within said substrate for accumulating photo-generated charge in said area;
a readout circuit comprising at least an output transistor formed on said substrate; and
,a self-aligned buried contact formed over a doped region in said substrate and between two structures on said substrate electrically connecting said imaging device, wherein said structures are selected from a transistor gate and an isolation region. - View Dependent Claims (94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 122, 124)
-
-
112. A method of forming a self-aligned buried contact in a CMOS imager, comprising the steps of:
-
providing a substrate including at least one transistor and at least one isolation region;
forming an protective layer over said substrate;
selectively removing at least a portion of said protective layer between a gate of said at least one transistor and another substrate feature selected from the group consisting of another transistor gate and said isolation region;
forming a continuously conductive layer in said self-aligned plug opening to form a self-aligned buried contact. - View Dependent Claims (113, 114, 115, 116, 117, 118, 119, 120, 121, 123, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139)
-
Specification