Method for wet etching of high k thin film at low temperature

• US 20030148625A1
• Filed: 03/18/2002
• Published: 08/07/2003
• Est. Priority Date: 02/01/2002
• Status: Active Grant

• Current Assignee: Grand Plastic Tech Corporation, Semiconductor Manufacturing International Corporation
• Original Assignee: Grand Plastic Tech Corporation, Semiconductor Manufacturing International Corporation
• Inventors: Wang, Chih-Cheng, Shih-Yi, Hsiao, Huang, Chih-Feng, Tao, Hun-Jan, Tsai, Ming-Huan, Perng, Baw-Ching, Tsui, Bing-Yue, Tsung-Kuei, Kang, Liang, Jann-Shyang, Ho, Hsieh Yue
• Granted Patent: US 7,115,526 B2
• Time in Patent Office: Days
• US Class Current: 438/745
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31641 Deposition of Zirconium oxides, e.g. ZrO2
• CPC Class Codes: H01L 21/31645 Deposition of Hafnium oxides, e.g. HfO2
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line

Abstract

The present invention discloses an electrode structure of a light emitted diode and manufacturing method of the electrodes. After formed a pn junction of a light emitted diode on a substrate, a layer of SiO2 is deposited on the periphery of the die of the LED near the scribe line of the wafer, then a transparent conductive layer is deposited blanketly, then a layer of gold or AuGe etc. is formed with an opening on the center of the die. After forming alloy with the semiconductor by heat treatment to form ohmic contact, a strip of aluminum (Al) is formed on one side of the die on the front side for wire bonding and to be the positive electrode of the LED. The negative electrode is formed on the substrate by metal contact. Another form of the electrode structure of the present invention is making both the positive and negative electrodes on the front side of the LED by etching the p-type semiconductor of the pn junction and forming a strip of negative electrode on the n-type semiconductor, the positive electrode is formed on the p-type semiconductor.

Claims

1. A method of high dielectric film wet etching, comprising the steps of:

Preparing a wafer having deposited a high dielectric film on silicon dioxide or poly-silicon;

Etching the high dielectric film with an etching agent by wet etching;

Rinsing the wafer with de-ionized water;

Drying the wafer;

5. A method according to claim 1,2,3 or 4, wherein the high dielectric film is Hafnium oxide (HfO₂)

6. A method according to claim 1,2,3 or 4, wherein the high dielectric film is Zirconium oxide (ZrO₂).

7. A method according to claim 1,2,3 or 4, wherein the etching agent is a mixture of hydrofluoric acid (HF) and perchloric acid (HClO₄).

8. A method according to claim 1,2,3 or 4, wherein the etching agent is a mixture of hydrofluoric acid (HF) and perbromic acid (HBrO₄).

9. A method according to claim 1,2,3 or 4, wherein the etching agent is a mixture of hydrofluoric acid (HF) and periodic acid (HIO₄).

10. A method according to claim 7,8 or 9, wherein the mixture has a volume ratio of HF:

HClO₄ (HBrO₄, HIO₄)=1;

50 to 1;

5000.

11. A method according to claim 7,8 or 9, wherein the mixture has a volume ratio of HF:

HClO₄ (HBrO₄,HIO₄)=1;

1000 to 1;

2500.

12. A method according to claim 1,2,3 or 4, wherein etching is performed at low temperature (0100).

13. A method according to claim 1,2,3 or 4, wherein etching is performed in a single wafer tool.

14. A method according to claim 1,2,3 or 4, wherein etching is performed in a batch type tool.

15. A method according to claim 1,2,3 or 4, wherein etching is performed in a clusters tool.

16. A method according to claim 1,2,3 or 4, wherein etching is performed in a stand alone tool.

17. A method according to claim 1,2,3 or 4, wherein the etch rate of HfO₂ of the etching agent is above 10A/min.

18. A method according to claim 1,2,3 or 4, wherein the etch rate of ZrO₂ of the etching agent is above 10A/min.

19. A method according to claim 1,2,3 or 4, wherein the etch rate of SiO₂ of the etching agent is below 10A/min.

20. A method according to claim 1,2,3 or 4, wherein the etch rate of the undoped silicon glass (USG) of the etching agent is below 10A/min.

21. A method according to claim 1,2,3 or 4, wherein the etch rate of BPSG of the etching agent is below 10A/min.

22. A method according to claim 1,2,3 or 4, wherein the etch rate of PSG of the etching agent is below 10A/min.

23. A method according to claim 1,2,3 or 4, wherein the etch rate of poly-Si of the etching agent is below 10A/min.

24. A method according to claim 1,2,3 or 4, wherein the etch rate of Si of the etching agent is below 10A/min.

2. A method of manufacturing a CMOS logic device with high dielectric gate, comprising the steps of:

Forming un-doped silicon glass (USG) in the shallow trench isolation or LOCOS, p-well and n-well region;

Deposition of a high dielectric film and forming a conductive layer of the gate;

Defining the gate pattern by lithography and etch the conductive layer outside the gate area;

Implanting an n⁻

and p⁻

dopant in the p-well and n-well to form a lightly doped in the source/drain region;

Deposition of a silicon nitride film and etching an isotropically to form a pair of silicon nitride side-walls;

Etching the high dielectric film to removed the high dielectric on the source/drain region by using an etching agent by wet etching;

Forming the highly doped source/drain by self aligned ion implantation using the gate and the side-wall as a mask;

Completing the back-end metalization process.

3. A method of manufacturing a high dielectric capacitor DRAM, comprising the steps of:

Forming transistors and lower electrode of a capacitor of a DRAM on a wafer, depositing high dielectric film as the insulating film of the capacitor;

Using lithography to form a photo resist pattern to protect the lower electrode and the high dielectric film on the lower electrode, then etch at low temperature to remove the high dielectric outside the lower electrode using an etching agent by wet etching;

Depositing a top electrode;

Completing the back-end metallization process.

4. A method of manufacturing a high dielectric capacitor, comprising the steps of:

Forming a lower electrode of a capacitor on a substrate, depositing a high dielectric film on the lower electrode as the insulating film of the capacitor;

Using lithography to form a photo-resist pattern to protect the lower electrode and the high dielectric on the lower electrode, then etch at low temperature to remove the high dielectric outside the lower electrode using an etching agent by wet etching;

Depositing a top electrode;

Completing the back-end metallization process.