Method and apparatus for timing and event processing in wireless systems

• US 20030149809A1
• Filed: 08/29/2002
• Published: 08/07/2003
• Est. Priority Date: 08/29/2001
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Moller, Thorkild Leth, Nielsen, Morten, Jensen, Poul R., Christiansen, Mogens
• Granted Patent: US 7,315,956 B2
• Time in Patent Office: Days
• US Class Current: 710/22
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 12/0859 with reload from main memory
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 2213/3814 Wireless link with a computer system port
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence
• CPC Class Codes: H04W 88/06 : adapted for operation in multiple networks or having at least two operational modes, e.g. multi-mode terminals
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 : in wire-line communication networks, e.g. low power modes or reduced link rate
• CPC Class Codes: Y02D 30/70 : in wireless communication networks
• CPC Class Codes: Y10S 331/02 : Phase locked loop having lock indicating or detecting means

Abstract

A digital baseband processor is provided for concurrent operation with different wireless systems. The digital baseband processor includes a digital signal processor for executing digital signal processor instructions, a microcontroller for executing microcontroller instructions, and a timing and event processor controlled by the digital signal processor and the microcontroller for executing timing-sensitive instructions. The timing and event processor includes a plurality of instruction sequencers for executing timing-sensitive instruction threads and a time base generator for generating timing signals for initiating execution of the instruction threads on each of the plurality of instruction sequencers.

Claims

1. A digital baseband processor comprising:

at least one main processor for executing instructions in a first instruction sequence; and

a timing and event processor coupled to said main processor for executing timing-sensitive instructions in a second instruction sequence, said timing and event processor comprising;

two or more instruction sequencers for executing threads of the second instruction sequence; and

a time base generator for generating timing signals for initiating execution of instructions on each of the two or more instruction sequencers.

2. A digital baseband processor as defined in claim 1, wherein said timing and event processor includes means for initiating time precise DMA transfers between components of the digital baseband processor.

3. A digital baseband processor as defined in claim 1, wherein said timing and event processor includes means for time precise enabling of a DMA channel in the digital baseband processor.

4. A digital baseband processor as defined in claim 1, wherein said timing and event processor includes means for generating a time precise interrupt to said main processor.

5. A digital baseband processor as defined in claim 1, wherein said timing and event processor includes means for generating a time precise trigger to another component of the digital baseband processor.

6. A digital baseband processor as defined in claim 1, wherein said timing and event processor includes means for generating time precise output signals.

7. A digital baseband processor as defined in claim 1, wherein said timing and event processor includes means for calibrating a low frequency clock with respect to a high frequency clock and generating a calibrated low frequency clock and a phase compensation signal.

8. A digital baseband processor as defined in claim 1, wherein said timing and event processor includes a power control circuit responsive to the time base generator for gating off the clock to modules in the digital baseband processor that are idle.

9. A digital baseband processor as defined in claim 1, wherein said timing and event processor further includes a memory for holding instructions and data for said two or more instruction sequencers.

10. A digital baseband processor as defined in claim 9, wherein said memory is multi-ported and wherein said timing and event processor further includes a memory access resolver for controlling access to the memory by said two or more instruction sequencers.

11. A digital baseband processor as defined in claim 1, wherein said timing and event processor further comprises and I/O conflict resolver for resolving conflicts in outputs produced by said two or more instruction sequencers and for generating an exception in response to a conflict.

12. A digital baseband processor as defined in claim 1, further comprising a DMA controller for processing DMA requests, wherein said timing and event processor includes a DMA interface for initiating time precise DMA transfers.

13. A digital baseband processor as defined in claim 12, wherein said timing and event processor further includes a DMA request resolver for resolving conflicts among DMA requests produced by said two or more instruction sequencers.

14. A digital baseband processor as defined in claim 1, wherein said timing and event processor further comprises a bus interface for coupling said two or more instruction sequencers to a processor bus.

15. A digital baseband processor as defined in claim 1, wherein said time base generator includes a clock calibration circuit for calibrating a relatively unstable low frequency clock with respect to a relatively stable high frequency clock and producing a calibrated low frequency clock.

16. A digital baseband processor as defined in claim 15, wherein said timing and event processor further comprises an absolute counter for counting the calibrated low frequency clock and producing programmable timing signals.

17. A digital baseband processor for concurrent operation with different wireless systems, comprising:

a digital signal processor for executing digital signal processor instructions;

a microcontroller for executing microcontroller instructions; and

a timing and event processor controlled by said digital signal processor and said microcontroller for executing timing-sensitive instructions, said timing and event processor comprising;

a plurality of instruction sequencers for executing timing-sensitive instruction threads; and

a time base generator for generating timing signals for initiating execution of the instruction threads on each of the plurality of instruction sequencers.

18. A method for generating timing signals for operating a wireless terminal in a wireless system having a wireless system time base, comprising:

generating a calibrated slow clock;

generating absolute time values by counting the calibrated slow clock to provide a unified time base; and

timing events in the wireless system based on the absolute time values of the unified time base independent of the wireless system time base.

19. A method as defined in claim 18, wherein the step of timing events comprises timing events in two or more wireless systems, each having a wireless system time base, based on the unified time base independent of the wireless system time bases.

20. A method as defined in claim 18, wherein the step of timing events comprises scheduling events relative to other events in response to delta-time values derived from a system clock.

21. A method as defined in claim 18, wherein the step of timing events comprises comparing a wait time contained in an instruction with the absolute time values and performing a specified operation when the wait time is equal to an absolute time value.

22. An apparatus for generating timing signals for operating a wireless terminal in a wireless system having a wireless system time base, comprising:

means for generating a calibrated slow clock;

means for generating absolute time values by counting the calibrated slow clock to provide a unified time base; and

means for timing events in the wireless system based on the absolute time values of the unified time base independent of the wireless system time base.

23. A method for generating a calibrated clock, comprising:

receiving a free-running fast clock;

receiving a free-running slow clock;

modifying the free-running slow clock to provide a calibrated slow clock having a specified frequency relationship to the fast clock; and

providing a phase compensation signal that represents a phase error in the calibrated slow clock.

24. A method as defined in claim 23, wherein the step of modifying the free-running slow clock comprises removing cycles from the free-running slow clock to provide the calibrated slow clock.

25. A method as defined in claim 24, wherein the step of modifying the free-running slow clock further comprises counting the number of fast clock cycles in a selected number of free-running slow clock cycles and determining a period with which cycles are removed from the free-running slow clock based on the specified frequency relationship and the number of fast clock cycles in the selected number of free-running slow clock cycles.

26. A method for generating a calibrated clock, comprising:

receiving a free-running fast clock;

receiving a free-running slow clock;

specifying a relationship between the fast clock and a calibrated slow clock;

counting the number of fast clock cycles in a selected number of free-running slow clock cycles to provide a comparison value;

removing cycles from the free-running slow clock to provide the calibrated slow clock, based on the specified relationship between the fast clock and the calibrated slow clock, and on the comparison value; and

providing a phase compensation signal that represents a phase error in the calibrated slow clock.

27. A method as defined in claim 26, wherein the step of providing a phase compensation signal comprises providing a number of fast clock cycles that represents the phase error.

28. Apparatus for generating a calibrated clock comprising:

means for receiving a free-running fast clock;

means for receiving a free-running slow clock;

means for modifying the free-running slow clock to provide a calibrated slow clock having a specified frequency relationship to the fast clock; and

means for providing a phase compensation signal that represents a phase error in the calibrated slow clock.

29. A method for performing DMA transfers in a baseband processor, comprising:

performing computations in a digital signal processor core;

generating timing signals in a timing and event processor; and

performing a DMA transfer in response to a request from the digital signal processor and in response to the timing signals from the timing and event processor to provide a timed DMA transfer.

30. A method as defined in claim 29, wherein the step of performing a DMA transfer comprises performing the DMA transfer on a DMA channel that is dedicated to the timing and event processor.

31. A baseband processor for wireless applications, comprising:

a digital signal processor core for performing digital signal computations;

a timing and event processor coupled to said digital signal processor core for executing timing-sensitive operations, said timing and event processor comprising a time base generator for generating timing signals, and a DMA control circuit for initiating a DMA request in response to a command from the digital signal processor core and the timing signals from the time base generator; and

a DMA controller for executing the DMA request to provide a timed DMA transfer.