DATA PROCESSING SYSTEM HAVING AN EXTERNAL DEVICE INTERFACE WITH ASSIGNED ADDRESSING

• US 20030149821A1
• Filed: 01/07/2003
• Published: 08/07/2003
• Est. Priority Date: 09/20/1994
• Status: Abandoned Application

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Matsui, Shigezumi, Narita, Susumu, Kawasaki, Ikuya, Nemoto, Masato
• Application Number:
  US10/337,631
• Publication Number:
  US 20030149821A1
• Time in Patent Office: Days
• US Class Current: 710/301
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

A microprocessor comprising a bus state controller and for use in a personal computer or the like. The bus state controller includes control registers such as wait controllers, and parallelly controls the interfaces of various semiconductor memories (ROM, burst ROM, SRAM, PSRAM, DRAM and synchronous RAM) and PC cards (memory and I/O cards). Also included in the bus state controller is a control register for controlling the time to set up PC card start signals where a synchronous DRAM(s) is configured. The address space of an external bus of the microprocessor is divided into a predetermined number of areas to which the semiconductor memories and PC cards are fixedly assigned. The microprocessor further comprises a memory management unit for converting an internally prepared logical address to a physical address.

Claims

1. A microprocessor comprising an interface circuit for permitting semiconductor memories and PC cards to be connected directly to said microprocessor.

2. A microprocessor according to claim 1, wherein said interface circuit generates a plurality of control signals to be output onto an external bus of said microprocessor;

wherein said semiconductor memories include a ROM, a burst ROM, an SRAM, a PSRAM, a DRAM and a synchronous DRAM; and

wherein said PC cards include a memory card and an I/O card.

3. A microprocessor according to claim 2, wherein said external bus has an address space divided into a plurality of areas assigned fixedly to predetermined semiconductor memories and PC cards, said microprocessor further comprising a memory management unit for converting an internal logical address to a physical address applicable to said external bus.

4. A microprocessor according to claim 3, wherein said external bus is capable of having at least part of said semiconductor-memories connected concurrently with said memory card and said I/O card to said microprocessor.

5. A microprocessor according to claim 4, wherein said I/O card functions either as an I/O device or a memory, and wherein the physical addresses in effect when said I/O card acts as the I/O device are assigned independently of those in effect when said I/O card functions as the memory.

6. A microprocessor according to claim 3, further comprising a bus state controller including registers for inter-face control between said semiconductor memories and said PC cards, said registers being used to set the types and the operating conditions of said semiconductor memories and said PC cards assigned to said areas.

7. A microprocessor according to claim 6, wherein at least part of said semiconductor memories and said PC cards have burst mode for consecutive access to a series of addresses, and wherein said bus state controller has an address generating circuit for use in said burst mode.

8. A microprocessor according to claim 7, wherein said bus state controller is a state machine.