Reconfigurable parallel look up table system

• US 20030149857A1
• Filed: 04/24/2002
• Published: 08/07/2003
• Est. Priority Date: 02/07/2002
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Stein, Yosef, Primo, Haim
• Granted Patent: US 6,829,694 B2
• Time in Patent Office: Days
• US Class Current: 711/206
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 9/345 of multiple operands or results addressing multiple banks G06F12/06

Abstract

A reconfigurable parallel look-up table system includes a memory; a plurality of look-up tables stored in the memory; a row index register for holding the values to be looked up in the look-up tables; a column index register for storing a value representing the starting address of the look-up tables stored in the memory; and an address translation circuit responsive to the column index register and the row index register to simultaneously generate an address for each value in the row index register to locate in parallel the function of those values in each look-up table.

Claims

1. A reconfigurable parallel look-up table system comprising:

a memory;

a plurality of look-up tables stored in said memory;

a row index register for holding the values to be looked up in said look-up tables;

a column index register for storing a value representing the starting address of each said look-up table stored in said memory; and

an address translation circuit responsive to said column index register and said row index register to simultaneously generate an address for each value in said row index register to locate in parallel the functions of those values in each look-up table.

2. The reconfigurable parallel look-up table system of claim 1 in which said address translation circuit includes a multiplier circuit for multiplying the value representing the starting address by the length of each column, and an adder circuit for combining the value in said row index register with the output of said multiplier circuit.

3. The reconfigurable parallel look-up table system of claim 1 in which said address translation circuit includes an OR circuit for combining said values in said row index register and said values in said column index register shifted toward the MSB by n bits in respect to the values in the row index register.

4. The reconfigurable parallel look-up table system of claim 1 in which said look-up tables are all the same size.