Method for fabricating a memory cell
First Claim
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1. A method for fabricating a memory cell, which comprises:
- in a first step, patterning at least one film of an electrically conductive layer to form strip-like sections on a semiconductor material that is selected from the group consisting of a semiconductor body and a semiconductor layer;
forming a doped region for a source and a doped region for a drain using a process selected from the group consisting of performing an implantation prior to the first step and diffusing dopant out of a material of the electrically conductive layer after the first step;
in a second step, forming a trench having sides between the strip-like sections of the electrically conductive layer such that the doped region for the source remains at one of the sides of the trench and the doped region for the drain remains at another one of the sides of the trench;
in a third step, applying a boundary layer, a memory layer and a boundary layer on top of one another over an entire surface of the semiconductor material; and
in a fourth step, introducing an electrically conductive material for a gate electrode into the trench and patterning the electrically conductive material to form at least one conductor track that is provided as a word line.
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Abstract
An electrically conductive layer or layer sequence preferably includes a metal-containing layer applied to a metal silicide or a polysilicon layer to reduce the resistance of buried bit lines. The layer or layer sequence has been patterned in strip form so as to correspond to the bit lines and is arranged on the source/drain regions of memory transistors having an ONO memory layer sequence and gate electrodes that are arranged in trenches. The metal silicide is preferably cobalt silicide, and the metal-containing layer is preferably tungsten silicide or WN/W. .
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Citations
8 Claims
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1. A method for fabricating a memory cell, which comprises:
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in a first step, patterning at least one film of an electrically conductive layer to form strip-like sections on a semiconductor material that is selected from the group consisting of a semiconductor body and a semiconductor layer;
forming a doped region for a source and a doped region for a drain using a process selected from the group consisting of performing an implantation prior to the first step and diffusing dopant out of a material of the electrically conductive layer after the first step;
in a second step, forming a trench having sides between the strip-like sections of the electrically conductive layer such that the doped region for the source remains at one of the sides of the trench and the doped region for the drain remains at another one of the sides of the trench;
in a third step, applying a boundary layer, a memory layer and a boundary layer on top of one another over an entire surface of the semiconductor material; and
in a fourth step, introducing an electrically conductive material for a gate electrode into the trench and patterning the electrically conductive material to form at least one conductor track that is provided as a word line. - View Dependent Claims (2, 3, 4)
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5. A method for fabricating a memory cell, which comprises:
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in a first step, fabricating at least one film of a patterning layer to form strip-like sections on a semiconductor material that is selected from the group consisting of a semiconductor body and a semiconductor layer;
in a second step, forming a trench having sides between the strip-like sections of the patterning layer so that regions of the semiconductor material serving as a source region and as a drain region remain at the sides of the trench;
in a third step, applying a boundary layer, a memory layer and a boundary layer on top of one another over an entire surface of the semiconductor material;
in a fourth step, introducing an electrically conductive material for a gate electrode into the trench;
in a fifth step, replacing the strip-like sections of the patterning layer with strip-like sections of an electrically conductive layer;
in a sixth step, applying at least one conductor track serving as a word line such that that the conductor track electrically contacts the electrically conductive material that has been introduced into the trench and such that the conductor track is electrically isolated from the strip-like sections of the electrically conductive layer; and
forming doped regions that serve as the source region and the drain region using a process selected from the group consisting of performing an implantation prior to the first step and diffusing dopant out of a material of the electrically conductive layer after the fifth step. - View Dependent Claims (6, 7, 8)
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Specification