CALIBRATION OF RESISTOR LADDER USING DIFFERENCE MEASUREMENT AND PARALLEL RESISTIVE CORRECTION

• US 20030151532A1
• Filed: 07/29/2002
• Published: 08/14/2003
• Est. Priority Date: 02/13/2002
• Status: Active Grant

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Inventors: Sanchez, Mario, Chen, Hsin-Shu, Song, Bang-Sup, Allen, Brian L., Hakkarainen, J. Mikko, Bacrania, Kantilal, Sung, Eric C.
• Granted Patent: US 6,628,216 B2
• Time in Patent Office: Days
• US Class Current: 341/120
• CPC Class Codes: H03M 1/165 in which two or more residues with respect to different reference levels in a stage are used as input signals for the next stage, i.e. multi-residue type
• CPC Class Codes: H03M 1/365 the voltage divider being a single resistor string

Abstract

A calibration system and method for a resistor ladder that employs relative measurement and adjustment between pairs of resistors. The system includes a resistor tree of complementary pairs of programmable resistors coupled to the resistor ladder, a measurement circuit that measures voltage differences between complementary pairs of programmable resistors, and control logic. The control logic controls the measurement circuit to measure a voltage difference between each complementary pair of programmable resistors and adjusts the relative resistance of each complementary pair of programmable resistors to equalize voltage. The measurement is facilitated by a sigma-delta ADC that converts a measured voltage difference into a bit stream. The programmable resistors are implemented with binary weighted resistors that are digitally adjusted one LSB at a time. Lower and upper adjustment thresholds may be employed to avoid unnecessary over-adjustments while maintaining a requisite level of accuracy.

Title:Calibration of Resistor Ladder Using DifferenceMeasurement and Parallel Resistive CorrectionInventor(s):Hsin-Shu Chen, Kantilal Bacrania, Eric C. Sung,J. Mikko Hakkarainen, Bang-Sup Song, Brian L. Allenand Mario Sanchez

Claims

1. A calibration system for a resistor ladder including N resistors, comprising:

a resistor tree of calibration resistors, coupled to the resistor ladder, the resistor tree including a plurality of branches wherein each branch comprises at least one pair of complementary programmable resistors coupled together at a common junction and wherein each programmable resistor of each branch is coupled in parallel with N/X resistors of the resistor ladder in which X is a positive integer starting at 2 for a first branch and incremented for each additional branch to N for a final branch and wherein a branch is included in the resistor tree only if N/X is an integer, the plurality of branches including the first branch with a pair of complementary programmable resistors each coupled in parallel with N/2 resistors of the resistor ladder and the final branch with N programmable resistors each coupled in parallel with a corresponding one of the resistors of the resistor ladder;

a measurement circuit, coupled to the resistor tree, that measures a voltage difference between a selected complementary pair of programmable resistors; and

control logic, coupled to the measurement circuit and the resistor tree, that controls the measurement circuit to measure a voltage difference between each complementary pair of programmable resistors and that adjusts the relative resistance of each complementary pair of programmable resistors to achieve a more equal voltage if the voltage difference is greater than a predetermined magnitude.

2. The resistor ladder calibration system of claim 1, wherein the resistance of and the current through the resistor tree of calibration resistors remains the same before and after each adjustment by the control logic.

3. The resistor ladder calibration system of claim 1, wherein the resistor tree of calibration resistors comprises a binary tree in which each successive branch includes twice the number of programmable resistors as a prior branch.

4. The resistor ladder calibration system of claim 1, wherein the control logic adjusts each complementary pair of programmable resistors by increasing resistance of a first by an adjust amount and by decreasing resistance of a second by the same adjust amount.

5. The resistor ladder calibration system of claim 4, wherein each programmable resistor comprises a binary weighted resistor subladder.

6. The resistor ladder calibration system of claim 5, wherein each binary weighted resistor subladder is programmed by a digital value and wherein the control logic adjusts the relative resistance by incrementing a first digital value by one least significant bit and by decrementing a second digital value by one least significant bit.

7. The resistor ladder calibration system of claim 4, further comprising:

each programmable resistance programmable via a digital resistance value;

a first memory, coupled to the control logic and the resistor tree, that stores a plurality of digital resistance values, each digital resistance value programming a resistance of a corresponding one of the programmable resistors of the resistor tree; and

a second memory, coupled to the first memory and the control logic, that stores a plurality of digital update values and wherein each of the plurality of digital update values corresponds to one of the plurality of digital resistance values.

8. The resistor ladder calibration system of claim 7, wherein the control logic adjusts a programmable resistor by replacing a digital resistance value in the first memory with a corresponding digital update value from the second memory.

9. The resistor ladder calibration system of claim 7, wherein the measurement circuit comprises:

an analog subtractor that measures a voltage difference between a selected complementary pair of programmable resistors; and

a sigma-delta converter, coupled to the analog subtractor, that provides a bit stream representative of the measured voltage difference.

10. The resistor ladder calibration system of claim 9, wherein the analog subtractor comprises a switched capacitor comparator.

11. The resistor ladder calibration system of claim 9, further comprising a counter, coupled to the sigma-delta converter, that counts bits having a predetermined binary value of the bit stream for a predetermined measurement interval and that provides a sum value.

12. The resistor ladder calibration system of claim 11, wherein the control logic includes adjust logic, coupled to the counter and the second memory, that converts the sum value to an adjust value and that increases one digital update value by the adjust value and decreases a complementary digital adjust value by the adjust value in the second memory for the measurement interval.

13. The resistor ladder calibration system of claim 12, wherein the adjust logic comprises:

digital compare logic, coupled to the counter, that compares the sum value with predetermined upper and lower thresholds and that sets the adjust value to zero if the sum value is within both thresholds, that sets the adjust value to one polarity if the upper threshold is reached and that sets the adjust value to an opposite polarity if the lower threshold is reached;

a digital adder, coupled to the digital compare logic and the second memory, that adds the adjust value to a first digital update value; and

a digital subtractor, coupled to the digital compare logic and the second memory, that subtracts the adjust value from a second digital update value that is complementary to the first digital update value.

14. The resistor ladder calibration system of claim 12, wherein the control logic conducts a sequential measurement cycle including performing a sequential series of measurement intervals to measure and adjust each complementary pair of programmable resistors of the resistor tree.

15. The resistor ladder calibration system of claim 14, wherein the control logic continuously repeats each sequential measurement cycle during operation.

16. The resistor ladder calibration system of claim 15, wherein the control logic asserts an update signal after each measurement cycle that causes each of the plurality of digital resistance values in the first memory to be replaced by a corresponding one of the plurality of digital update values in the second memory.

17. The resistor ladder calibration system of claim 1, wherein the resistor ladder is used in a differential manner and wherein the N calibrated resistors of the resistor ladder comprises at least half the number of total ladder resistors.

18. A method of calibrating a resistor ladder including N resistors, comprising:

measuring a voltage difference between a pair of ladder resistances having a common junction and including the same number of ladder resistors;

adjusting a complementary pair of programmable resistors, each coupled in parallel with a corresponding one of the pair of ladder resistances, to reduce the voltage difference to within a predetermined magnitude; and

repeating said measuring and adjusting for each complementary pair of programmable resistors of a resistor tree during a measurement cycle, the resistor tree including a plurality of branches wherein each branch comprises at least one pair of complementary programmable resistors coupled together at a common junction and wherein each programmable resistor of each branch is coupled in parallel with N/X resistors of the resistor ladder in which X is a positive integer starting at 2 for a first branch and incremented for each additional branch to N for a final branch and wherein a branch is included in the resistor tree only if N/X is an integer, the plurality of branches including the first branch with a pair of complementary programmable resistors each coupled in parallel with N/2 resistors of the resistor ladder and the final branch with N programmable resistors each coupled in parallel with a corresponding one of the resistors of the resistor ladder.

19. The method of claim 18, further comprising maintaining overall resistance of the resistor ladder before and after each measuring and adjusting.

20. The method of claim 18, further comprising continuously repeating the measurement cycle during operation of an underlying system.

21. The method of claim 18, wherein said measuring comprises:

subtracting a first voltage from a second voltage to provide the voltage difference;

converting the voltage difference to a bit stream using a delta-sigma analog to digital converter; and

counting the number of bits of the bit stream having a predetermined binary value during a predetermined measurement interval to provide a sum value.

22. The method of claim 21, wherein said adjusting comprises:

converting the sum value to an adjust value; and

increasing resistance of a first of the complementary pair of programmable resistors by the adjust value and decreasing resistance of a second of the complementary pair of programmable resistors by the adjust value.

23. The method of claim 22, wherein said converting comprises:

comparing the sum value to upper and lower thresholds;

setting the adjust value to zero if the sum value is within both thresholds;

setting the adjust value to one polarity if the upper threshold is reached; and

setting the adjust value to an opposite polarity if the lower threshold is reached.

24. The method of claim 23, wherein said setting the adjust value further comprises setting a magnitude of the adjust value based on a difference between the sum value and a target value between the upper and lower thresholds.

25. The method of claim 23, the programmable resistors of the resistor tree being programmable by digital values, wherein said increasing resistance of a first of the complementary pair of programmable resistors comprises incrementing a first digital value by a least significant bit and wherein said decreasing resistance of a second of the complementary pair of programmable resistors comprises decrementing a second and complementary digital value by a least significant bit.