Modular memory device

• US 20030151959A1
• Filed: 01/13/2003
• Published: 08/14/2003
• Est. Priority Date: 08/14/2000
• Status: Active Grant

• Current Assignee: Innovative Memory Systems, Inc. (Wi-LAN Inc.)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Lee, Thomas, Bosch, Derek, Johnson, Mark, Farmwald, P., Tringali, J.
• Granted Patent: US 6,867,992 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Abstract

In one embodiment, a modular memory device is presented comprising a substrate, a memory array fabricated above the substrate, and first and second circuitry fabricated on the substrate and under the memory array. The first and second circuitry allow the modular memory device to interface with first and second varieties of host devices, respectively. In another embodiment, a modular memory device is presented comprising a substrate, a memory array fabricated above the substrate, memory array support circuitry fabricated on the substrate, and logic circuitry fabricated on the substrate and under the memory array.

Claims

1. A modular memory device comprising:

a substrate;

a memory array fabricated above the substrate;

first circuitry fabricated on the substrate and under the memory array, the first circuitry allowing the modular memory device to interface with a first variety of host devices; and

second circuitry fabricated on the substrate and under the memory array, the second circuitry allowing the modular memory device to interface with a second variety of host devices.

2. The invention of claim 1, wherein the memory array comprises a two-dimensional memory array.

3. The invention of claim 1, wherein the memory array comprises a plurality of layers of memory cells stacked vertically above one another in a single chip.

4. The invention of claim 1, wherein the memory array comprises a plurality of write-once memory cells.

5. The invention of claim 1, wherein the memory array comprises a plurality of field-programmable memory cells.

6. The invention of claim 1 further comprising:

a support element carrying the substrate; and

an electrical connector carried by the support element and coupled with the first and second circuitry.

7. The invention of claim 1, wherein the first variety of host devices operates in accordance with a CompactFlash protocol, and wherein the second variety of host devices operates in accordance with a SmartMedia protocol.

8. The invention of claim 1, wherein the first circuitry implements an interrupt management function for the first variety of host devices, and wherein the second circuitry implements an interrupt management function for the second variety of host devices.

9. The invention of claim 1, wherein the first and second circuitry are part of a device interface unit.

10. A modular memory device comprising:

a substrate;

a memory array fabricated above the substrate;

memory array support circuitry fabricated on the substrate; and

logic circuitry fabricated on the substrate and under the memory array.

11. The invention of claim 10, wherein the memory array support circuitry comprises row and column decoder circuits.

12. The invention of claim 10, wherein the memory array support circuitry is under the memory array.

13. The invention of claim 10, wherein the logic circuitry comprises first circuitry operative to allow the modular memory device to interface with a first variety of host devices.

14. The invention of claim 13, wherein the logic circuitry additionally comprises second circuitry operative to allow the modular memory device to interface with a second variety of host devices.

15. The invention of claim 14, wherein the first variety of host devices operates in accordance with a CompactFlash protocol, and wherein the second variety of host devices operates in accordance with a SmartMedia protocol.

16. The invention of claim 14, wherein the first circuitry implements an interrupt management function for the first variety of host devices, and wherein the second circuitry implements an interrupt management function for the second variety of host devices.

17. The invention of claim 10, wherein the memory array comprises a two-dimensional memory array.

18. The invention of claim 10, wherein the memory array comprises a plurality of layers of memory cells stacked vertically above one another in a single chip.

19. The invention of claim 10, wherein the memory array comprises a plurality of write-once memory cells.

20. The invention of claim 10, wherein the memory array comprises a plurality of field-programmable memory cells.