Method and system for calibrating an oscillator circuit using a network based time reference

• US 20030152177A1
• Filed: 02/14/2002
• Published: 08/14/2003
• Est. Priority Date: 02/14/2002
• Status: Active Grant

• Current Assignee: Itron, Inc.
• Original Assignee: Itron, Inc.
• Inventors: Dusenberry, Robert V., Cahill-OʼBrien, Barry
• Granted Patent: US 6,639,957 B2
• Time in Patent Office: Days
• US Class Current: 375/354
• CPC Class Codes: H04J 3/0664 unidirectional timestamps
• CPC Class Codes: H04J 3/0667 Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays arrangements for monitoring round trip delays in packet switching networks H04L43/0864
• CPC Class Codes: H04L 2027/0024 at the receiver end
• CPC Class Codes: H04L 2027/0083 Signalling arrangements
• CPC Class Codes: H04L 27/0014 Carrier regulation of chaotic carriers H04L27/001; for multicarrier receivers H04L27/2657
• CPC Class Codes: H04L 69/329 in the application layer [OSI layer 7]
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A method and system of compensating for reference frequency drift utilizes time stamps from a networked reference clock to adjust a local crystal oscillator of a communications device. In an example embodiment, a microprocessor arrangement of the communications device obtains a synchronization time stamp from a networked clock arrangement and synchronizes the local oscillator clock and a clock circuit of the microprocessor with the time stamp. After a predetermined time duration has transpired, a calibration time stamp is obtained from the network clock and the difference between the calibration time stamp and the current time of the clock circuit is extracted. The clock circuit and the networked clock arrangement are then synchronized and the local crystal oscillator is adjusted for crystal aging as a function of the difference between the calibration time stamp and the current time of the clock circuit.

Claims

1. A method of compensating for reference frequency drift in a communications device, the communications device having a microprocessor arrangement and a local oscillator circuit adapted to generate a reference frequency signal and operate synchronously with a clock circuit of the microprocessor arrangement, the method comprising:

a) generating a clock circuit time reference for the clock circuit by dividing the reference frequency signal by a divisor;

b) obtaining a synchronization time stamp from a networked reference clock arrangement operably connected to the microprocessor arrangement and synchronizing the clock circuit to the synchronization time stamp;

c) obtaining a calibration time stamp from the networked reference clock arrangement after a predetermined time duration has transpired from synchronization of the clock circuit and comparing the calibration time stamp to a current time of the clock circuit; and

d) synchronizing the current time of the clock circuit with the calibration time stamp and adjusting the local oscillator circuit as a function of a time variation between the calibration time stamp and the current time of the clock circuit.

2. The method of claim 1, wherein the local oscillator circuit is continuously compensated for frequency drift by repeating steps c) and d).

3. The method of claim 2, wherein the predetermined time duration is defined by the steps of:

counting a number of repeatable attributes associated with the reference frequency signal after synchronizing the clock circuit; and

upon reaching a target number of repeatable attributes, determining a time duration corresponding to the target number.

4. The method of claim 3, wherein adjusting the local oscillator comprises:

correlating a frequency drift value to the time variation between the calibration time stamp and the current time of the clock circuit; and

responsive to the frequency drift value, adjusting the oscillator circuit so as to synchronize the oscillator circuit with the calibration time stamp obtained from the networked reference clock arrangement, wherein the frequency drift value is a function of the target number of repeatable attributes counted in the predetermined time duration.

5. The method of claim 3 wherein counting the repeatable attributes includes counting clock edges.

6. The method of claim 1, wherein the networked reference clock arrangement includes an atomic clock arrangement.

7. The method of claim 1, wherein the network reference clock arrangement includes at least one server arrangement adapted to operate with a network time protocol software application.

8. The method of claim 1, wherein obtaining the synchronization and calibration time stamps from the networked reference clock arrangement includes obtaining the time stamps via a wireless communications channel.

9. The method of claim 4, wherein the frequency drift value is about one PPM (parts per million) for each second that the current time varies from the calibration time stamp.

10. A system for compensating for reference frequency drift in a communications device, the communications device having a microprocessor arrangement and a local oscillator circuit adapted to generate a reference frequency signal and operate synchronously with a clock circuit of the microprocessor arrangement, the system comprising:

a) means for generating a clock circuit time reference for the clock circuit by dividing the reference frequency signal by a divisor;

b) means, responsive to generation of the clock circuit time reference, for obtaining a synchronization time stamp from a networked reference clock arrangement operably connected to the microprocessor arrangement and for synchronizing the clock circuit to the synchronization time stamp;

c) means, responsive to a predetermined time duration transpiring from synchronization of the clock circuit, for obtaining a calibration time stamp from the networked reference clock arrangement and comparing the calibration time stamp to a current time of the clock circuit; and

d) means, responsive to the calibration time stamp comparison, for synchronizing the current time of the clock circuit with the calibration time stamp and adjusting the local oscillator circuit as a function of a time variation between the calibration time stamp and the current time of the clock circuit.

11. The system of claim 10, further comprising:

means, responsive to synchronizing the clock circuit, for counting a number of repeatable attributes associated with the reference frequency signal; and

means, responsive to reaching a target number of repeatable attributes, for determining a time duration corresponding to the target number.

12. The system of claim 10, further comprising means for obtaining the synchronization and calibration time stamps via communications lines from the networked reference clock arrangement, the communication lines being selected from the group consisting of fiber optic cables, coaxial cables and public service telephone network lines.

13. The system of claim 10, further comprising means for obtaining the synchronization and calibration stamps via a wireless communications channel.

14. A reference frequency compensation circuit arrangement having a local crystal oscillator circuit adapted to generate a reference frequency signal, the frequency compensation circuit arrangement comprising:

a dividing circuit adapted to divide the reference frequency signal so as to generate a clock circuit time reference; and

a microprocessor arrangement operably connected to a networked reference clock arrangement and having a clock circuit, the microprocessor arrangement adapted to obtain a synchronization time stamp from the networked reference clock arrangement and synchronize the clock circuit time reference to the synchronization time stamp, the microprocessor arrangement also adapted to obtain a calibration time stamp from the networked reference clock arrangement after a predetermined time duration from the synchronization of the clock circuit has transpired and adapted to compare the calibration time stamp to a current time stamp of the clock circuit, the microprocessor arrangement further adapted to synchronize the current time reference of the clock circuit with the calibration time stamp and adjust the local oscillator circuit as a function of a time variation between the calibration time stamp and the current time of the clock circuit.

15. The frequency compensation circuit arrangement of claim 14, wherein the dividing circuit further comprises a counting circuit, the counting circuit adapted to be initialized by the microprocessor arrangement after synchronization of the clock circuit with the synchronization time stamp and adapted to count a number of repeatable attributes associated with the reference frequency signal until a target number of repeatable attributes is reached, the microprocessor arrangement further adapted to determine a time duration corresponding to the target number.

16. The frequency compensation circuit arrangement of claim 15, wherein the microprocessor arrangement is adapted to correlate a frequency drift value to a time variation between the calibration time stamp and the current time reference, the microprocessor arrangement further adapted to adjust the local oscillator circuit so as to synchronize the oscillator circuit with the calibration time stamp obtained from the reference clock arrangement, wherein the frequency drift value is a function of the target number of repeatable attributes counted in the predetermined time duration.

17. The frequency compensation circuit arrangement of claim 15, wherein the counting circuit is adapted to count a number of clock edges in the reference frequency signal until reaching the target number, and wherein the microprocessor arrangement is adapted to convert the target number of clock edges to the predetermined time duration.

18. The frequency compensation circuit arrangement of claim 17, further including a digital-to-analog converting circuit operably connected to the oscillator circuit and adapted to convert a correction signal from the microprocessor arrangement into a reference frequency compensation signal.

19. The frequency compensation circuit arrangement of claim 18, wherein the networked clock arrangement and the microprocessor arrangement include a network time protocol application adapted to retrieve the synchronization and calibration time stamps from a network.

20. The frequency compensation circuit arrangement of claim 19, further comprising means for enabling the microprocessor arrangement to communicate via radio frequency signals to the network to obtain the time stamps.

21. The frequency compensation circuit arrangement of claim 14, wherein the local crystal oscillator circuit includes a temperature compensated crystal oscillator circuit.

22. The frequency compensation circuit arrangement of claim 16, wherein the frequency drift value is about one PPM (parts per million) for each second that the current time varies from the calibration time stamp.