Delay locked loop synthesizer with multiple outputs and digital modulation
First Claim
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11. A circuit for producing two output signals having frequency Fout and differing by a phase shift, comprising:
- a delay locked loop having a plurality of addressable tap outputs;
a tap selection circuit that selects a first sequence of tap addresses Cja; and
an adder that adds a normalized phase shift component Φ
=K.C (a desired phase shift) to the first sequence of tap addresses Cja to produce a second sequence of tap addresses Cjb, where K.C=Fout/Fref, and Fref being a reference clock frequency.
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Abstract
A delay locked loop circuit (200) in which multiple outputs are produced. A single delay line (24) is shared among multiple tap selection circuits (256A, 265B, 265C). Fixed phase shifts (412) can be introduced between multiple outputs. A modulating signal can be used in the tap selection processing to produce digital amplitude, frequency and/or phase modulation.
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Citations
80 Claims
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11. A circuit for producing two output signals having frequency Fout and differing by a phase shift, comprising:
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a delay locked loop having a plurality of addressable tap outputs;
a tap selection circuit that selects a first sequence of tap addresses Cja; and
an adder that adds a normalized phase shift component Φ
=K.C (a desired phase shift) to the first sequence of tap addresses Cja to produce a second sequence of tap addresses Cjb, where K.C=Fout/Fref, and Fref being a reference clock frequency. - View Dependent Claims (12, 13, 14)
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15. A circuit for producing two output signals differing by a phase shift, comprising:
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a delay locked loop having a plurality of addressable delay line tap outputs, the delay locked loop synthesizing the output signals at a frequency Fout, with K.C=Fout/Fref, and Fref being a reference clock frequency;
a tap selection circuit that selects a sequence of tap addresses Cja;
a first multiplexer, wherein the sequence of tap addresses Cja are applied to a plurality of inputs of the first multiplexer to produce a first output signal Fouta; and
a second multiplexer, wherein the sequence of tap addresses Cja are added to a delay factor α
K.C where α
is a desired phase shift and applied to a plurality of inputs of the second multiplexer to produce a second output signal Foutb. - View Dependent Claims (16, 17, 18, 19)
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20. A digital modulator, comprising:
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a delay locked loop having a delay line with a plurality of tap outputs; and
a tap selection processor that selects a sequence of time varying tap addresses C(t) that vary in accordance with a modulating signal m(t). - View Dependent Claims (21, 22, 23, 24, 25, 26, 27)
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28. A digital phase modulator, comprising:
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a delay locked loop having a delay line with a plurality of tap outputs;
a tap selection processor that selects a sequence of time varying tap addresses Cj(t) that vary in time in accordance with a modulating signal m(t); and
a multiplexer circuit, and wherein the time varying tap addresses Cj(t) are applied to the multiplexer circuit to select a time varying sequence of tap outputs as a phase modulated output signal Fout(t). - View Dependent Claims (29, 30, 31, 32, 33)
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34. A digital frequency modulator, comprising:
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a delay locked loop having a delay line with a plurality of tap outputs;
a tap selection processor that selects a sequence of time varying tap addresses Cj(t) that vary in time in accordance with a modulating signal m(t); and
a multiplexer circuit, and wherein the time varying tap addresses Cj(t) are applied to the multiplexer circuit to select a time varying sequence of tap outputs as a frequency modulated output signal Fout(t). - View Dependent Claims (35, 36, 37, 38, 39)
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40. A digital amplitude modulator, comprising:
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a delay locked loop having a delay line with a plurality of tap outputs;
a tap selection processor that selects a sequence of time varying tap addresses Cj(t) that vary in time in accordance with a modulating signal m(t); and
a multiplexer circuit, and wherein the time varying tap addresses Cj(t) are applied to the multiplexer circuit to select a time varying sequence of tap outputs as an amplitude modulated output signal Fout(t). - View Dependent Claims (41, 42, 43, 44, 45, 46, 47, 48)
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49. A method of producing multiple output frequencies using a delay locked loop having a delay line with a plurality of tap outputs, comprising:
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selecting a first sequence of the tap outputs according to a first timing to produce a first output signal Fout1; and
selecting a second sequence of the tap outputs according to a second timing to produce a second output signal Fout2. - View Dependent Claims (50, 51)
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52. A method of producing two output signals differing by a phase shift in a delay locked loop circuit having a delay line with a plurality of addressable tap outputs, comprising:
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selecting a first sequence of tap addresses Cja; and
adding a phase shift component Φ
to the first sequence of tap addresses Cja to produce a second sequence of tap addresses Cjb. - View Dependent Claims (53, 54, 55)
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56. A method of producing two output signals differing by a phase shift using a delay locked loop having a plurality of addressable delay line tap outputs, comprising:
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selecting a sequence of tap addresses Cja;
applying the sequence of tap addresses Cja to a plurality of inputs of a first multiplexer to produce a first output signal Fouta; and
applying the sequence of tap addresses Cja to a plurality of inputs of a second multiplexer to produce a second output signal Foutb;
wherein Fout1 differs from Fout2 by the phase shift, and wherein the phase shift is determined by a constant difference in address location selected by the sequence of tap addresses Cja between the first and second multiplexers. - View Dependent Claims (1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 57, 58, 60)
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58-1. The apparatus according to claim 56, wherein the phase shift corresponds to ±
- 90 degrees.
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61. A method of providing digital modulation, comprising:
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providing a delay locked loop having a delay line with a plurality of tap outputs;
receiving a modulating signal m(t); and
selecting a sequence of time varying tap addresses C(t) that vary in accordance with the modulating signal m(t). - View Dependent Claims (62, 63, 64, 65, 66, 67, 68)
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69. A method of providing digital phase modulation in a delay locked loop having a delay line with a plurality of tap outputs, comprising:
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selecting a sequence of time varying tap addresses Cj(t) that vary in time in accordance with a modulating signal m(t); and
applying the time varying tap addresses Cj(t) to a multiplexer circuit to select a time varying sequence of tap outputs as a phase modulated output signal Fout(t). - View Dependent Claims (70)
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71. A method of providing digital frequency modulation in a delay locked loop circuit having a delay line with a plurality of tap outputs, comprising:
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selecting a sequence of time varying tap addresses Cj(t) that vary in time in accordance with a modulating signal m(t); and
applying the time varying tap addresses Cj(t) to a multiplexer circuit to select a time varying sequence of tap outputs as a frequency modulated output signal Fout(t). - View Dependent Claims (72)
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73. A method of providing digital amplitude modulation in a delay locked loop circuit having a delay line with a plurality of tap outputs, comprising:
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selecting a sequence of time varying tap addresses Cj(t) that vary in time in accordance with a modulating signal m(t); and
applying the time varying tap addresses Cj(t) to a multiplexer circuit to select a time varying sequence of tap outputs as an amplitude modulated output signal Fout(t). - View Dependent Claims (74, 75, 76, 77, 78)
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79. A method of selecting delay line taps to produce an output signal from a delay locked loop, comprising:
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computing an tap address P.Q where P is an integer part and Q is a fractional part; and
selecting a delay line tap address of P during a portion of an operational cycle and of P+1 during a remainder of the operational cycle, with the regularity of selection of P and P+1 determined by an algorithm that establishes an average value of the tap address as approximately P.Q. - View Dependent Claims (80)
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Specification