Optical exchange method, apparatus and system for facilitating data transport between WAN, SAN and LAN and for enabling enterprise computing into networks

• US 20030152182A1
• Filed: 08/22/2001
• Published: 08/14/2003
• Est. Priority Date: 08/22/2000
• Status: Abandoned Application

• Current Assignee: Pai B. Anand, Srinivasan Krishnaswami, Terence Chui
• Original Assignee: Pai B. Anand, Srinivasan Krishnaswami, Terence Chui
• Inventors: Krishnaswami, Srinivasan, Chui, Terence, Pai, B. Anand
• Application Number:
  US09/935,800
• Publication Number:
  US 20030152182A1
• Time in Patent Office: Days
• US Class Current: 375/372
• CPC Class Codes: H04J 2203/006 Fault tolerance and recovery
• CPC Class Codes: H04J 2203/0082 Interaction of SDH with non-ATM protocols
• CPC Class Codes: H04J 3/062 Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers pulse-stuffing H04J3/07; asynchronous-synchronous conversion H04L5/24; speed conversion H04L25/05; speed conversion in computers G06F5/06
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04J 3/08 Intermediate station arrangements, e.g. for branching, for tapping-off
• CPC Class Codes: H04J 3/1617 carrying packets or ATM cells
• CPC Class Codes: H04L 12/46 Interconnection of networks
• CPC Class Codes: H04Q 11/0071 Provisions for the electrical-optical layer interface

Abstract

An integrated circuit device for use in forming a communication interface for an enterprise server including a system controller, at least one CPU, a system bus communicatively interconnecting the controller and the CPU, a system memory, a first optical interface for facilitating data transport between the device and SONET based networks, and a second optical interface for facilitating data transport between the device and ethernet/Fibre Channel based networks. The integrated circuit device is comprised of an interface including a SONET-in engine for receiving SONET input data from the first optical interface and for extracting synchronous payload envelopes (SPE) therefrom, a deframer for extracting data packets from the incoming SPE, a plurality of ethernet/Fibre Channel (E/FC) ports selectively programmable to function as either a GbE port or an FC port for communicating with the second optical interface, a generic interface unit (GIU) for communicating data signals to and from the system bus, and a packet engine (PE) responsive to routing tables and operative to sort and forward each extracted data packet IP packet or FC frame via the BIC to a particular one of the plurality of GbE/FC ports.

Claims

1. Transmission system including a synchronizer for forming a multiplex signal, a device for conveying the multiplex signal, and a desynchronizer which comprises at least:

a buffer store for buffering transport unit data contained in the signal;

a write address generator for controlling the writing of the data in the buffer store;

a control arrangement for forming a control signal for the write address generator from the signal;

a read address generator for controlling the reading of the data from the buffer store;

a difference circuit for forming difference values between the addresses of the write and read address generators,

a generating circuit for generating from a difference signal a read clock signal which is applied to the read address generator,

a correction circuit, and

a combiner circuit, wherein the control arrangement is provided for determining the offset of at least one transport unit in the signal and for applying the determined offset to the correction circuit which correction circuit is used for forming the phase difference between a lower-order transport unit and a higher-order transport unit, and in that the combiner circuit is provided for providing the difference signal to the generating circuit by combining a correction value resulting from the subtraction of the two phase differences, and a difference value from the difference circuit.